# US 7,610,449 B2 · Apparatus and method for saving power in a trace cache

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- Number: US 7,610,449 B2
- Document ID: US7610449B2
- Status: Granted
- Kind: B2
- Application number: 11/538,458
- Filed: 2006-10-04
- Published: 2008-04-10
- Granted: 2009-10-27
- Earliest claimed: 2006-10-04
- Assignees: International Business Machines Corporation
- Inventors: Gordon T. Davis; Richard W. Doing; John D. Jabusch; M V V Anil Krishna; Brett Olsson; Eric F. Robinson; Sumedh W. Sathaye; Jeffrey R. Summers
- Web page: https://patentgrep.com/patent/US7610449B2

## CPC

- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 9/3808: {for instruction reuse, e.g. trace cache, branch target cache}
- G06F 2212/1028: Power efficiency
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Power is conserved by guiding access to lines stored in the cache and lowering cache clock speed relative to the central processor clock speed.

## Claims

### Claim 1

Apparatus comprising:
a computer system central processor;
layered memory operatively coupled to said central processor and accessible thereby, said layered memory having a level one cache storing in interchangeable locations both standard cache lines and trace lines; and
a trace cache controller having a directory guiding access to lines stored in said level one cache, the directory having both tag data and size data for stored cache lines, the controller optimizing power requirements in accessing stored cache lines by reading data associated with valid instruction entries;
said trace cache controller operating level one cache processes at a clock speed which is a fraction of the clock speed of said central processor.

### Claim 2 (depends on 1)

Apparatus according to claim 1 wherein said level one cache stores instruction data in blocks of predetermined size, the predetermined size being a fraction of the storage capability of a single cache line.

### Claim 3 (depends on 1)

Apparatus according to claim 1 wherein the logical structure of said level one cache is divided into a plurality of physical arrays, and further wherein said controller accesses a number of physical arrays limited to those necessary to retrieve relevant instruction data.

### Claim 4 (depends on 1)

Apparatus according to claim 1 further comprising a branch history table function predicting branching within instructions to be stored as traces prior to storage of such traces.

### Claim 5

Method comprising:
coupling together a computer system central processor and layered memory accessible by the central processor;
selectively storing in interchangeable locations of a level one cache of the layered memory both standard cache lines and trace lines;
operating trace cache processes at a clock speed which is a fraction of the clock speed of the central processor;
storing tag data and size data for each stored cache line; and
optimizing power requirements in accessing stored cache lines by reading data associated with valid instruction entries.

### Claim 6 (depends on 5)

Method according to claim 5 wherein the selective storing of cache lines stores instruction data in blocks of predetermined size, the predetermined size being a fraction of the storage capability of a single cache line.

### Claim 7 (depends on 5)

Method according to claim 5 wherein the logical structure of the level one cache is divided into a plurality of physical arrays, and further comprising accessing a number of physical arrays limited to those necessary to retrieve relevant instruction data.

### Claim 8 (depends on 5)

Method according to claim 5 further comprising predicting branching within instructions to be stored as traces prior to storage of such traces.

### Claim 9

Programmed method comprising:
coupling together a computer system central processor and layered memory accessible by the central processor, the layered memory including a level one cache;
selectively storing in interchangeable locations of the level one cache of the layered memory both standard cache lines and trace lines;
operating trace cache processes at a clock speed which is a fraction of the clock speed of the central processor;
storing tag data and size data for each stored cache line; and
optimizing power requirements in accessing stored cache lines by reading data associated with valid instruction entries.

### Claim 10 (depends on 9)

Programmed method according to claim 9 wherein the selective storing of cache lines stores instruction data in blocks of predetermined size, the predetermined size being a fraction of the storage capability of a single cache line.

### Claim 11 (depends on 9)

Programmed method according to claim 9 wherein the logical structure of the level one cache is divided into a plurality of physical arrays, and further comprising accessing a number of physical arrays limited to those necessary to retrieve relevant instruction data.

### Claim 12 (depends on 9)

Programmed method according to claim 9 further comprising predicting branching within instructions to be stored as traces prior to storage of such traces.