# US 7,610,448 B2 · Obscuring memory access patterns

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- Number: US 7,610,448 B2
- Document ID: US7610448B2
- Status: Granted
- Kind: B2
- Application number: 11/646,642
- Filed: 2006-12-27
- Published: 2008-07-03
- Granted: 2009-10-27
- Earliest claimed: 2006-12-27
- Assignees: Intel Corporation
- Inventors: Mark Buxton; Ernie Brickell; Quinn A. Jacobson; Hong Wang; Baiju Patel
- Web page: https://patentgrep.com/patent/US7610448B2

## CPC

- G06F 12/0842: for multiprocessing or multitasking
- G06F 9/30047: {Prefetch instructions; cache control instructions}
- G06F 12/1458: {by checking the subject access rights}
- G06F 21/52: during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow}
- G06F 21/78: to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

For each memory location in a set of memory locations associated with a thread, setting an indication associated with the memory location to request a signal if data from the memory location is evicted from a cache; and in response to the signal, reloading the set of memory locations into the cache.

## Claims

### Claim 1

A method comprising
for each memory location in a set of memory locations associated with a thread, setting an indication associated with the memory location to request a signal if data from the memory location is evicted from a cache; and
in response to the signal, reloading the set of memory locations into the cache.

### Claim 2 (depends on 1)

The method of claim 1 further comprising loading the set of memory locations into the cache in at least one of
a random order; and
a predetermined order.

### Claim 3 (depends on 1)

The method of claim 1 wherein the signal further comprises an interrupt, the method further comprising registering a handler to respond to the signal.

### Claim 4 (depends on 1)

The method of claim 1 wherein the set of memory locations further comprises a set of memory locations having data, at least in part, private to the thread.

### Claim 5 (depends on 2)

The method of claim 2 wherein the signal comprises an interrupt, and wherein reloading the memory locations into the cache further comprises logic of a processor reloading the set of memory locations into the cache in at least one of
a random order; and
a predetermined order.

### Claim 6 (depends on 3)

The method of claim 3 wherein reloading the set of memory locations into the cache further comprises the handler reloading the set of memory locations into the cache in at least one of
a random order; and
a predetermined order.

### Claim 7 (depends on 3)

The method of claim 3 wherein setting the indication associated with the memory location further comprises setting an attribute bit associated with the cache line of the data from the memory location to a predetermined value, the method further comprising logic of a processor detecting the eviction of data from the memory location from the cache and generating the interrupt.

### Claim 8 (depends on 1)

The method of claim 1 further comprising the thread detecting that the thread has resumed execution following a context switch and the thread reloading the set of memory locations into the cache at least in part in response to the detecting.

### Claim 9

A system comprising
a processor;
a memory communicatively coupled with the processor, further comprising a program thread (thread), where for each memory location in a set of memory locations associated with the thread, the thread is to set an indication associated with the memory location to request a signal if data from the memory location is evicted from a cache; and
in response to the signal, to reload the set of memory locations into the cache.

### Claim 10 (depends on 9)

The system of claim 9 wherein the thread is further to load the set of memory locations into the cache in at least one of
a random order; and
a predetermined order.

### Claim 11 (depends on 9)

The system of claim 9 wherein the signal further comprises an interrupt, the thread further to register a handler to respond to the signal.

### Claim 12 (depends on 9)

The system of claim 9 wherein the set of memory locations further comprises a set of memory locations having data, at least in part, private to the thread.

### Claim 13 (depends on 10)

The system of claim 10 wherein the signal comprises an interrupt, and wherein reloading the set of memory locations into the cache further comprises logic of a processor reloading the set of memory locations into the cache in at least one of
a random order; and
a predetermined order.

### Claim 14 (depends on 11)

The system of claim 11 wherein reloading the set of memory locations into the cache further comprises the handler reloading the set of memory locations into the cache in at least one of
a random order; and
a predetermined order.

### Claim 15 (depends on 11)

The system of claim 11 wherein setting the indication associated with the memory location further comprises setting an attribute bit associated with the cache line of the data from the memory location to a predetermined value, and wherein the system further comprises logic to detect the eviction of data from the memory location from the cache and to generate the interrupt.

### Claim 16 (depends on 9)

The system of claim 9 wherein the thread is further to detect that the thread has resumed execution following a context switch and the to reload the set of memory locations into the cache at least in part in response to the detecting.

### Claim 17

A tangible machine readable medium having stored thereon data that when accessed by a machine causes it to perform a method, the method comprising
for each memory location in a set of memory locations associated with a thread, setting an indication associated with the memory location to request a signal if data from the memory location is evicted from a cache; and
in response to the signal, reloading the set of memory locations into the cache.

### Claim 18 (depends on 17)

The machine readable medium of claim 17 wherein the method further comprises loading the set of memory locations into the cache in at least one of
a random order; and
a predetermined order.

### Claim 19 (depends on 17)

The machine readable medium of claim 17 wherein the signal further comprises an interrupt, the method further comprising registering a handler to respond to the signal.

### Claim 20 (depends on 17)

The machine readable medium of claim 17 wherein the set of memory locations further comprises a set of memory locations having data, at least in part, private to the thread.

### Claim 21 (depends on 18)

The machine readable medium of claim 18 wherein the signal comprises an interrupt, and wherein reloading the set of memory locations into the cache further comprises logic of a processor reloading the set of memory locations into the cache in at least one of
a random order; and
a predetermined order.

### Claim 22 (depends on 19)

The machine readable medium of claim 19 wherein reloading the set of memory locations into the cache further comprises the handler reloading the set of memory locations into the cache in at least one of
a random order; and
a predetermined order.

### Claim 23 (depends on 19)

The machine readable medium of claim 19 wherein setting the indication associated with the memory location further comprises setting an attribute bit associated with the cache line of the data from the memory location to a predetermined value, the method further comprising logic of a processor detecting the eviction of data from the memory location from the cache and generating the interrupt.

### Claim 24 (depends on 19)

The machine readable medium of claim 19 wherein the method further comprises the thread detecting that the thread has resumed execution following a context switch and the thread reloading the set of memory locations into the cache at least in part in response to the detecting.