# US 7,610,439 B2 · Method and system for hardware implementation of resetting an external two-wired EEPROM > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,610,439 B2 - Document ID: US7610439B2 - Status: Granted - Kind: B2 - Application number: 11/673,348 - Filed: 2007-02-09 - Published: 2008-08-14 - Granted: 2009-10-27 - Earliest claimed: 2007-02-09 - Assignees: Broadcom Corporation - Inventors: Jonathan F. Lee; Xiaogang Zhu - Web page: https://patentgrep.com/patent/US7610439B2 ## CPC - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without intervention from a central processing unit (CPU). The resetting may occur via a virtual CPU. Another aspect of the invention may have the signal generation and EEPROM resetting occurring via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM. ## Claims ### Claim 1 A method for controlling an electrically erasable programmable read only memory (EEPROM), the method comprising: generating a clock signal at a frequency suitable for operation of said EEPROM; and resetting said EEPROM via said generated clock signal and a hardware generated data signal without intervention from a central processing unit (CPU). ### Claim 2 (depends on 1) The method according to claim 1, wherein said resetting occurs via a virtual CPU. ### Claim 3 (depends on 2) The method according to claim 2, wherein said virtual CPU is integrated within a finite state machine. ### Claim 4 (depends on 1) The method according to claim 1, wherein said generating is controlled via a virtual CPU. ### Claim 5 (depends on 1) The method according to claim 1, wherein said generating is controlled via a finite state machine. ### Claim 6 (depends on 1) The method according to claim 1, wherein said resetting occurs via a finite state machine. ### Claim 7 (depends on 1) The method according to claim 1, wherein said generating of said clock signal occurs utilizing a frequency counter. ### Claim 8 (depends on 7) The method according to claim 7, wherein said frequency counter detects a signal frequency from a clock source having a higher frequency. ### Claim 9 A system for controlling an EEPROM, the system comprising: one or more circuits for generating a clock signal suitable for operation of said EEPROM; and said one or more circuits resets said EEPROM via said generated clock signal and a hardware generated data signal, without intervention from a central processing unit (CPU). ### Claim 10 (depends on 9) The system according to claim 9, wherein said one or more circuits comprise a virtual central processing unit (VCPU), which is utilized for said resetting of said EEPROM. ### Claim 11 (depends on 10) The system according to claim 10, wherein said virtual CPU is integrated within a finite state machine. ### Claim 12 (depends on 9) The system according to claim 9, wherein said one or more circuits comprises a virtual CPU which controls said generation of said clock signal. ### Claim 13 (depends on 9) The system according to claim 9, wherein said one or more circuits comprises a finite state machine that controls said generation of said clock signal. ### Claim 14 (depends on 9) The system according to claim 9, wherein said one or more circuits comprises a finite state machine that controls said resetting of said EEPROM. ### Claim 15 (depends on 9) The system according to claim 9, wherein said one or more circuits comprises a frequency counter that is utilized for said generation of said clock signal. ### Claim 16 (depends on 15) The system according to claim 15, wherein said frequency counter detects a signal frequency from a clock source having a higher frequency. ### Claim 17 A machine-readable storage having stored thereon, a computer program having at least one code section for resetting an EEPROM, the at least one code section being executable by a machine for causing the machine to perform steps comprising: generating a clock signal suitable for operation of said EEPROM; and resetting said EEPROM via said generated clock signal and a hardware generated data signal without intervention from a central processing unit (CPU). ### Claim 18 (depends on 17) The machine-readable storage according to claim 17, wherein said at least one code section comprises code for generating a reset condition utilizing a virtual central processing unit (VCPU). ### Claim 19 (depends on 18) The machine-readable storage according to claim 18, wherein said at least one code section comprises code for integrating said virtual CPU within a finite state machine. ### Claim 20 (depends on 17) The machine-readable storage according to claim 17, wherein said at least one code section comprises code for controlling said generating via a virtual CPU. ### Claim 21 (depends on 17) The machine-readable storage according to claim 17, wherein said at least one code section comprises code for said resetting occurs via a finite state machine. ### Claim 22 (depends on 17) The machine-readable storage according to claim 17, wherein said at least one code section comprises code for generating said clock signal utilizing a frequency counter. ### Claim 23 (depends on 17) The machine-readable storage according to claim 17, wherein said at least one code section comprises code for detecting a signal frequency from a clock source having a higher frequency.