# US 7,610,435 B2 · Nonvolatile memory device employing a write completion flag table

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- Number: US 7,610,435 B2
- Document ID: US7610435B2
- Status: Granted
- Kind: B2
- Application number: 10/598,307
- Filed: 2005-02-25
- Published: 2008-01-31
- Granted: 2009-10-27
- Earliest claimed: 2004-02-27
- Assignees: Panasonic Corporation
- Inventors: Masahiro Nakanishi; Tomoaki Izumi; Tetsushi Kasahara; Kazuaki Tamura; Kiminori Matsuno; Manabu Inoue
- Web page: https://patentgrep.com/patent/US7610435B2

## CPC

- G06F 11/1441: {Resetting or repowering}
- G06F 11/1435: {using file system or storage system metadata}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A writing completion flag table that stores a writing completion flag corresponding to a predetermined storage, such as a cluster or a physical block, is stored in a non-volatile control memory. When completion of data writing into a predetermined storage is detected, a write completion flag is written in the corresponding address of the storage on the write completion flag table. Thus, it is possible to recognize that data has been written normally. Even when the flag indicating completion of writing into a page of the writing unit of the main storage memory cannot be written, it is possible to improve the writing reliability.

## Claims

### Claim 1

A semiconductor memory device, comprising:
a non-volatile main storage memory including a plurality of physical blocks, each physical block having a plurality of storage capacity units composed of a data region in a first storage capacity and a management region;
an address management information storage that stores address management information of said main storage memory and a block status of each physical block indicating whether data stored in the block is valid or not;
a non-volatile control memory that stores a writing completion flag table which is provided to said main storage memory every second storage capacity smaller than said first storage capacity and consists of writing completion flags placed when data writing is completed to each of said second storage capacity; and
a controller that performs read/write control for said main storage memory in accordance with a direction of data read/write from a host and for performing update control for said address management information storage part and said non-volatile control memory.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1, wherein
said second storage capacity is a cluster size, and
said non-volatile control memory records the writing completion flag table by writing completion flags of at least one bit for every cluster size prescribed by a file system of the host.

### Claim 3 (depends on 1)

The semiconductor memory device according to claim 1, wherein
said second storage capacity is a sector size, and
said non-volatile control memory records the writing completion flag table by writing completion flags of at least one bit for every sector size prescribed by a file system of the host.

### Claim 4 (depends on 1)

The semiconductor memory device according to claim 1, wherein
said non-volatile control memory has a higher writing-rate than that of said non-volatile main storage memory.

### Claim 5 (depends on 1)

The semiconductor memory device according to claim 1, wherein
said controller includes a memory map of the writing completion flag table at initialization or factory shipment, based on a preliminarily stored second storage capacity unit.

### Claim 6 (depends on 1)

The semiconductor memory device according to claim 1, wherein
said controller includes a memory map of the writing completion flag table at initialization or factory shipment, based on a second storage capacity unit transferred from the host.

### Claim 7 (depends on 1)

The semiconductor memory device according to claim 1, wherein
said non-volatile main storage memory comprises a multi-valued NAND flash memory.

### Claim 8 (depends on 1)

The semiconductor memory device according to claim 1, wherein
said address management information storage includes a physical region management table that stores conditions for every storage capacity unit of said main storage memory; and an address conversion table that converts an address designated by a file system of the host into an address of a storage capacity unit of said main storage memory.

### Claim 9 (depends on 1)

The semiconductor memory device according to claim 1, wherein
said control memory comprises a ferroelectric random access memory (FeRAM).

### Claim 10 (depends on 1)

The semiconductor memory device according to claim 1, wherein
said control memory comprises a magnetic random access memory (MRAM).

### Claim 11 (depends on 1)

The semiconductor memory device according to claim 1, wherein
said control memory comprises an ovonic unified memory (OUM).

### Claim 12 (depends on 1)

The semiconductor memory device according to claim 1, wherein
said control memory comprises a resistance RAM (RRAM).