# US 7,610,431 B1 · Configuration space compaction > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,610,431 B1 - Document ID: US7610431B1 - Status: Granted - Kind: B1 - Application number: 11/250,731 - Filed: 2005-10-14 - Granted: 2009-10-27 - Earliest claimed: 2005-10-14 - Assignees: Sun Microsystems, Inc. - Inventors: John Watkins; Ola Tørudbakken; John Petry; Michelle L Wong; Ravinandan R Buchamwandla - Web page: https://patentgrep.com/patent/US7610431B1 ## CPC - G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In an interconnect apparatus for interconnecting at least one host to at least a plurality of presentation registers provide a presentation interface for the device to the host. The interconnect apparatus includes memory for holding the presentation registers and a governor operable to manage the presentation registers in the memory. ## Claims ### Claim 1 An interconnect apparatus for interconnecting at least one host to at least one device that includes a plurality of presentation registers that reside in the interconnect apparatus, wherein the presentation registers: provide a presentation interface for the device to the host, the interconnect apparatus comprising memory for holding the presentation registers and a governor operable to manage the presentation registers in the memory, and comprise soft-configurable registers and hard-wired registers, wherein the interconnect apparatus enables software to modify the presentation registers to define, control, and access a status of one or more devices, and wherein the governor polls presentation layer access requests from one or more remote hosts seeking read or write access and foundation layer resource blocks seeking status updates. ### Claim 2 (depends on 1) The interconnect apparatus of claim 1, wherein the governor is operable to configure and/or control access to the presentation registers. ### Claim 3 (depends on 2) The interconnect apparatus of claim 2, wherein the interconnect apparatus is operable to interconnect multiple hosts to at least one device, the device provides a plurality of functions, respective sets of one or more presentation registers are associated with respective functions, and the governor is operable to support device virtualization according to an allocation of the respective functions to respective ones of the multiple hosts. ### Claim 4 (depends on 1) The interconnect apparatus of claim 1, wherein the governor comprises hard-wired logic for managing access to the presentation registers in the memory. ### Claim 5 (depends on 1) The interconnect apparatus of claim 1, wherein the governor is operable to provide error management in respect of the presentation registers. ### Claim 6 (depends on 1) The interconnect apparatus of claim 1, wherein the governor is operable to provide reset control in respect of the presentation registers. ### Claim 7 (depends on 1) The interconnect apparatus of claim 1, wherein the governor is at least partially integral to an interconnect device. ### Claim 8 (depends on 7) The interconnect apparatus of claim 7 wherein the governor is integral to an interconnect device. ### Claim 9 (depends on 7) The interconnect apparatus of claim 7, wherein the governor comprises hard-wired logic. ### Claim 10 (depends on 1) The interconnect apparatus of claim 1, wherein the memory is integral to an interconnect device. ### Claim 11 (depends on 1) The interconnect apparatus of claim 1, wherein the memory comprises SRAM. ### Claim 12 (depends on 1) The interconnect apparatus of claim 1, wherein the memory comprises DRAM. ### Claim 13 (depends on 1) The interconnect apparatus of claim 1, wherein at least one hard-wired register mirrors a presentation register in memory. ### Claim 14 (depends on 1) The interconnect apparatus of claim 1, wherein at least one bus connected to an interconnect device is a PCI bus. ### Claim 15 (depends on 1) The interconnect apparatus of claim 1, wherein at least one bus connected to an interconnect device is a PCI-E bus. ### Claim 16 (depends on 1) The interconnect apparatus of claim 1, wherein write masks are provided in the memory to selectively prevent remote host modification of read only fields of presentation registers. ### Claim 17 (depends on 1) The interconnect apparatus of claim 1, wherein the memory is configured to include non-shared presentation registers. ### Claim 18 (depends on 1) The interconnect apparatus of claim 1, wherein the memory is configured to include shared presentation registers. ### Claim 19 A computer system comprising an interconnect apparatus for interconnecting at least one host to at least one device and providing a plurality of presentation registers, wherein the presentation registers reside in the interconnect apparatus, wherein the presentation registers provide a presentation interface for the device to the host, the interconnect apparatus comprising memory for holding the presentation registers and a governor operable to manage the presentation registers in the memory, and comprise soft-configurable registers and hard-wired registers, wherein the interconnect apparatus enables software to modify the presentation registers to define, control, and access a status of one or more devices, and wherein the governor polls presentation layer access requests from one or more remote hosts seeking read or write access and foundation layer resource blocks seeking status updates. ### Claim 20 A method of interconnecting at least one host to at least one device via an interconnect apparatus, the method comprising maintaining in memory in the interconnect apparatus a plurality of presentation providing a presentation interface for the device to the host and managing the presentation registers in the memory, wherein the presentation registers: provide a presentation interface for the device to the host, the interconnect apparatus comprising memory for holding presentation registers and a governor operable to manage the presentation registers in the memory, and comprise soft-configurable registers and hard-wired registers, wherein the interconnect apparatus enables software to modify the presentation registers to define, control, and access a status of one or more devices, and wherein the governor polls presentation layer access requests from one or more remote hosts seeking read or write access and foundation layer resource blocks seeking status updates. ### Claim 21 (depends on 20) The method of claim 20, comprising configuring and/or controlling access to the presentation registers. ### Claim 22 (depends on 20) The method of claim 20, comprising interconnecting multiple hosts to at least one device, wherein the device provides a plurality of functions and respective sets of one or more presentation registers are associated with respective functions, the method further comprising supporting device virtualization according to an allocation of the respective functions to respective ones of the multiple hosts.