# US 7,610,425 B2 · Approach for managing interrupt load distribution > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,610,425 B2 - Document ID: US7610425B2 - Status: Granted - Kind: B2 - Application number: 11/499,027 - Filed: 2006-08-03 - Published: 2007-02-22 - Granted: 2009-10-27 - Earliest claimed: 2005-08-22 - Assignees: Sun Microsystems, Inc. - Inventors: Ethan Solomita; Sunay Tripathi - Web page: https://patentgrep.com/patent/US7610425B2 ## CPC - G06F 13/24: using interrupt (G06F13/32 takes precedence) - G06F 9/4812: {by interrupt, e.g. masked} - G06F 9/5083: {Techniques for rebalancing the load in a distributed system} - G06F 11/00: Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00) - G06F 11/3024: {where the computing system component is a central processing unit [CPU]} - G06F 11/3433: {for load management (allocation of a server based on load conditions G06F9/505; load rebalancing G06F9/5083; redistributing the load in a network by a load balancer H04L67/1029)} - G06F 11/3466: {Performance evaluation by tracing or monitoring} - G06F 2209/508: Monitor - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method and apparatus for distributing multiple interrupts among multiple processors is disclosed. According to one embodiment, an interrupt daemon monitors the interrupt load among the processors that results from an initial mapping of the interrupts to the processors. The interrupt daemon determines whether there is a sufficient imbalance of the interrupts among the processors. If so, the interrupt daemon triggers a reassignment routine that generates a new mapping of the interrupts among the processors, and if not, the interrupt daemon goes to sleep for a specified time period. If the new mapping produces a sufficient improvement in the distribution of interrupts among the processors, based on the same criteria used to detect the imbalance, the new mapping is used by the central hub for subsequent distribution of interrupts to the processors. However, if the new mapping does not provide a sufficient improvement, the original mapping continues to be used. ## Claims ### Claim 1 A method for managing interrupt load distribution in a system comprising a plurality of processors, the method comprising: monitoring a load of a device operatively connected to the plurality of processors; determining a mapping for the device that specifies at least two interrupt channels mapped to at least two of the plurality of processors; determining that a number of interrupt channels supported by the device is less than the number of interrupt channels specified in the mapping; in response to determining that the number of interrupt channels supported by the device is less than the number of interrupt channels specified in the mapping: designating a particular processor of the plurality of processors as a managing processor to receive interrupts on a particular interrupt channel, wherein the particular interrupt channel is used by the device to send interrupts; receiving, by the managing processor, interrupts from the device on the particular interrupt channel; and distributing, by the managing processor, the interrupts to the other processors of the plurality of processors. ### Claim 2 (depends on 1) The method of claim 1, wherein the device sends interrupts using only the particular interrupt channel, and wherein the method further comprises: designating the particular interrupt channel as a managed interrupt channel. ### Claim 3 (depends on 1) The method of claim 1, wherein distributing by the managing processor the interrupts to the other processors of the plurality of processors comprises only sending the interrupts to a set of processors identified in the mapping. ### Claim 4 (depends on 3) The method of claim 3, wherein at least one processor in the set of processors handles interrupts from only the device. ### Claim 5 (depends on 3) The method of claim 3, wherein a user designates at least one processor in the set of processors as reserved to handle interrupts from only the device. ### Claim 6 (depends on 1) The method of claim 1, wherein at least one of the interrupts comprises a plurality of tasks, and wherein the plurality of tasks are distributed among the other processors of the plurality of processors. ### Claim 7 (depends on 6) The method of claim 6, wherein distributing the plurality of tasks among the other processors of the plurality of processors comprises: determining that a particular task in the plurality of tasks is associated with a particular task category, wherein a task category identifies one or more tasks having common characteristics; and based upon the particular task category for the particular task, assigning the particular task to a certain processor of the plurality of processors. ### Claim 8 (depends on 1) The method of claim 1, wherein the device is a network interface. ### Claim 9 A machine-readable storage medium comprising a set of instructions which when executed by a machine, causes the machine to perform the following operations: monitoring a load of a device operatively connected to a plurality of processors in the machine; determining a mapping for the device that specifies at least two interrupt channels mapped to at least two of the plurality of processors; determining that a number of interrupt channels supported by the device is less than the number of interrupt channels specified in the mapping; in response to determining that the number of interrupt channels supported by the device is less than the number of interrupt channels specified in the mapping: designating a particular processor of the plurality of processors as a managing processor to receive interrupts on a particular interrupt channel, wherein the particular interrupt channel is used by the device to send interrupts; receiving, by the managing processor, interrupts from the device on the particular interrupt channel; and distributing, by the managing processor, the interrupts to the other processors of the plurality of processors. ### Claim 10 (depends on 9) The machine-readable storage medium of claim 9, wherein the device sends interrupts using only the particular interrupt channel, and wherein the set of instructions cause the one or more processors to further perform on operations of: designating the particular interrupt channel as a managed interrupt channel. ### Claim 11 (depends on 9) The machine-readable storage medium of claim 9, wherein distributing, by the managing processor, the interrupts to the other processors of the plurality of processors comprises only sending the interrupts to a set of processors identified in the mapping. ### Claim 12 (depends on 11) The machine-readable storage medium of claim 11, wherein at least one processor in the set of processors handles interrupts from only the device. ### Claim 13 (depends on 11) The machine-readable storage medium of claim 11, wherein a user designates at least one processor in the set of processors as reserved to handle interrupts from only the device. ### Claim 14 (depends on 9) The machine-readable storage medium of claim 9, wherein at least one of the interrupts comprises a plurality of tasks, and wherein the plurality of tasks are distributed among the other processors of the plurality of processors. ### Claim 15 (depends on 14) The machine-readable storage medium of claim 14, wherein distributing the plurality of tasks among the other processors of the plurality of processors comprises: determining that a particular task in the plurality of tasks is associated with a particular task category, wherein a task category identifies one or more tasks having common characteristics; and based upon the particular task category for the particular task, assigning the particular task to a certain processor of the plurality of processors. ### Claim 16 (depends on 9) The machine-readable storage medium of claim 9, wherein the device is a network interface.