# US 7,610,325 B2 · System(s), method(s), and apparatus for detecting end of slice groups in a bitstream

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- Number: US 7,610,325 B2
- Document ID: US7610325B2
- Status: Granted
- Kind: B2
- Application number: 11/092,209
- Filed: 2005-03-29
- Published: 2006-10-05
- Granted: 2009-10-27
- Earliest claimed: 2005-03-29
- Assignees: Broadcom Corporation
- Inventors: Chhavi Kishore; Jagannath Sathyanarayana Shastry
- Web page: https://patentgrep.com/patent/US7610325B2

## CPC

- H04N 19/174: the region being a slice, e.g. a line of blocks or a group of blocks
- H04N 19/61: in combination with predictive coding
- H04N 19/70: characterised by syntax aspects related to video coding, e.g. related to compression standards
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

Presented herein are system(s), method(s), and apparatus for detecting end of slice groups in a video bitstream. In one embodiment, there is presented a circuit for extracting a data structure from one or more data words. The circuit comprises a multiplexer, a bit pointer, a first logic circuit, and a comparator. The multiplexer provides one or more bits from the one or more data words. The bit pointer points to the bits following the provided one or more bits in the one or more data words. The first logic circuit examines at least portions of the data words for an end of data structure code, the at least portions comprising the one or more bits, and provides an indicator indicating the position of the end of data structure code. The comparator compares the indicator to where the bit pointer points.

## Claims

### Claim 1

A circuit for extracting a data structure from one or more data words, said circuit comprising:
a multiplexer for providing one or more bits from the one or more data words;
a bit pointer for pointing to bits following the provided one or more bits in the one or more data words;
a first logic circuit for examining at least portions of the data words for an end of data structure code, the at least portions comprising the one or more bits, and providing an indicator indicating the position of the end of data structure code; and
a comparator for comparing the indicator to where the bit pointer points.

### Claim 2 (depends on 1)

The circuit of claim 1, further comprising:
a second logic circuit for incrementing the bit pointer to point to the bit following the provided one or more bits.

### Claim 3 (depends on 2)

The circuit of claim 2, wherein the comparator provides a signal to the second logic circuit when the indicator and where the bit pointer points are equal.

### Claim 4 (depends on 3)

The circuit of claim 3, wherein the signal prevents the second logic from incrementing the bit pointer.

### Claim 5 (depends on 3)

The circuit of claim 3, wherein the second signal causes the second logic circuit to increments the bit pointer to point to the next byte.

### Claim 6 (depends on 1)

The circuit of claim 1, wherein the data words comprise 256 bits.

### Claim 7 (depends on 1)

The circuit of claim 1, wherein the at least a portion of the data words comprises smaller data words, and wherein the circuit further comprises:
another multiplexer for dividing the data words into smaller data words.

### Claim 8 (depends on 7)

The circuit of claim 7, further comprising:
a queue for sequentially providing the data words to the another multiplexer.

### Claim 9 (depends on 1)

The circuit of claim 1, further comprising:
a variable length code decoder for decoding the one or more bits.

### Claim 10 (depends on 1)

The circuit of claim 1, wherein the data structure is a slice group.

### Claim 11 (depends on 1)

The circuit of claim 1, further comprising:
a barrel shifter for providing the at least a portions of the data words to the first logic.

### Claim 12 (depends on 1)

The circuit of claim 1, wherein the barrel shifter further comprises:
a first shift register for storing a first at least a portion;
a second shift register for storing a second at least a portion; and
wherein the first shift register provides the first at least a portion to the first logic circuit.

### Claim 13

A circuit for extracting a data structure from one or more data words, said circuit comprising:
a multiplexer for providing one or more bits from the one or more data words;
a bit pointer for pointing to bits following the provided one or more bits in the one or more data words;
a first logic circuit for examining at one least portion of the one or more data words for an end of data structure code, the at least one portion comprising the one or more bits, and providing an indicator indicating the position of the end of data structure code; and
a comparator for comparing the indicator to where the bit pointer points.

### Claim 14

A circuit for extracting a data structure from a plurality of data words, said circuit comprising:
a multiplexer for providing one or more bits from the plurality of data words;
a bit pointer for pointing to bits following the provided one or more bits in the plurality of data words;
a first logic circuit for examining at least portions of the plurality of data words for an end of data structure code, the at least portions comprising the one or more bits, and providing an indicator indicating the position of the end of data structure code; and
a comparator for comparing the indicator to where the bit pointer points.