# US 7,610,163 B2 · Method of controlling quality for a print controller > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,610,163 B2 - Document ID: US7610163B2 - Status: Granted - Kind: B2 - Application number: 11/951,213 - Filed: 2007-12-05 - Published: 2008-04-10 - Granted: 2009-10-27 - Earliest claimed: 2002-12-02 - Assignees: Silverbrook Research Pty Ltd - Inventors: Gary Shipton; Simon Robert Walmsley - Web page: https://patentgrep.com/patent/US7610163B2 ## CPC - G06F 21/73: by creating or determining hardware identification, e.g. serial numbers - B41J 2/04505: {aiming at correcting alignment} - B41J 2/04508: {aiming at correcting other parameters} - B41J 2/0451: {for detecting failure, e.g. clogging, malfunctioning actuator} - B41J 2/04528: {aiming at warming up the head} - B41J 2/04541: {Specific driving circuit} - B41J 2/04543: {Block driving} - B41J 2/04563: {detecting head temperature; Ink temperature} - B41J 2/04573: {Timing; Delays} - B41J 2/04586: {controlling heads of a type not covered by groups B41J2/04575 - B41J2/04585, or of an undefined type} - G06F 21/554: {involving event detection and direct action} - G06F 21/57: Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities - G06F 21/575: {Secure boot} - G06F 21/64: Protecting data integrity, e.g. using checksums, certificates or signatures - G06F 21/71: to assure secure computing or processing of information - G06F 21/74: operating in dual or compartmented mode, i.e. at least one secure mode - G06F 21/78: to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00) - H03K 5/1252: Suppression or limitation of noise or interference (specially adapted for transmission systems H04B15/00, H04L25/08) - H04N 1/405: Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels - B41J 2202/20: Modules - Y10S 707/99933: Query processing, i.e. searching - Y10S 707/99939: Privileged access - Y10T 29/49401: Fluid pattern dispersing device making, e.g., ink jet - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - B41J: TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract A method performed by a quality assurance integrated circuit for a print controller, the quality assurance integrated circuit comprising a memory; a system clock for generating a clock signal; clock trim circuitry for trimming the frequency of the clock signal; and a processor. the method includes, in the processor, in response to receiving an external signal, determining the number of cycles of the clock signal during a predetermined number of cycles of the external signal or the number of cycles of the external signal during a predetermined number of cycles of the clock signal and to output the determined number of cycles to an external circuit; and in response to receiving a trim value based on the determined number of cycles from the external circuit, storing the trim value in the memory and controlling the clock trim circuitry to trim the frequency of the clock signal using the trim value. ## Claims ### Claim 1 A method performed by a quality assurance integrated circuit for a print controller, the quality assurance integrated circuit comprising a memory; a system clock having a ring oscillator for generating a clock signal; clock trim circuitry for trimming the frequency of the clock signal generated by the system clock; and a processor, wherein the method includes, in the processor: in response to receiving an external signal, determining the number of cycles of the clock signal during a predetermined number of cycles of the external signal or the number of cycles of the external signal during a predetermined number of cycles of the clock signal and to output the determined number of cycles to an external circuit; in response to receiving a trim value based on the determined number of cycles from the external circuit, storing the trim value in the memory; and controlling the clock trim circuitry to trim the frequency of the clock signal generated by the ring oscillator using the trim value. ### Claim 2 (depends on 1) The method according to claim 1, wherein the memory incorporates non-volatile memory, wherein the method includes storing the trim value in the non-volatile memory. ### Claim 3 (depends on 2) The method according to claim 2, where the non-volatile memory is flash RAM, wherein the method includes storing, using a flash write, the trim value to the non-volatile memory. ### Claim 4 (depends on 1) The method according to claim 1, wherein the clock trim circuitry incorporates a register, wherein the method includes, in the processor, loading the trim value from the memory into register. ### Claim 5 (depends on 1) The method according to claim 1, wherein the method includes storing the trim value permanently in the integrated circuit. ### Claim 6 (depends on 1) The method according to claim 1, wherein the quality assurance integrated circuit includes at least one fuse, wherein the method includes, in the processor, blowing the at least one fuse upon outputting the determined number of cycles to the external circuit, thereby preventing the subsequently received and stored trim value from being changed. ### Claim 7 (depends on 1) The method according to claim 1, wherein the quality assurance integrated circuit comprises a digital to analog converter, wherein the method includes converting the stored trim value to a voltage and supply the voltage to an input of the ring oscillator, thereby to control the frequency of the clock signal generated by the ring oscillator. ### Claim 8 (depends on 1) The method according to claim 1, wherein the method includes operating the integrated circuit under conditions in which the signal for which the number of cycles is being determined is at a considerably higher frequency than the other signal. ### Claim 9 (depends on 8) The method according to claim 8, wherein the method includes operating the integrating circuit when a ratio of the number of cycles determined and the predetermined number of cycles is greater than about 2. ### Claim 10 (depends on 9) The method according to claim 9, wherein the ratio is greater than about 4. ### Claim 11 (depends on 1) The method according to claim 1, disposed in a package having an external pin, wherein the method includes receiving the external signal via the external pin. ### Claim 12 (depends on 11) The method according to claim 11, wherein the pin is a serial communication pin configurable for serial communication when the trim value is being set. ### Claim 13 (depends on 1) The method according to claim 1, wherein in the method includes compensating the trim value based upon a temperature of the integrated circuit during the determination of the number of cycles.