# US 7,610,160 B2 · Integrated circuit tester information processing system

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- Number: US 7,610,160 B2
- Document ID: US7610160B2
- Status: Granted
- Kind: B2
- Application number: 11/857,272
- Filed: 2007-09-18
- Published: 2009-03-19
- Granted: 2009-10-27
- Earliest claimed: 2007-09-18
- Assignees: Globalfoundries Inc.
- Inventors: Sushant S. Suryagandh; Judy Xilin An
- Web page: https://patentgrep.com/patent/US7610160B2

## CPC

- G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)}
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- G01R 31/3025: {Wireless interface with the DUT}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for operating an integrated circuit tester information processing system includes measuring current information from test structures for an integrated circuit having dual stress liners; selecting currents from the current information or stored current information; deriving a scaling factor with the currents for a stress contribution based on an active area of a circuit element in the integrated circuit; and correlating the stress contribution with the integrated circuit.

## Claims

### Claim 1

A method for operating an integrated circuit tester information processing system comprising:
measuring current information from test structures for an integrated circuit having dual stress liners;
selecting currents from the current information or stored current information;
deriving a scaling factor with the currents for a stress contribution based on an active area of a circuit element in the integrated circuit; and
correlating the stress contribution with the integrated circuit.

### Claim 2 (depends on 1)

The method as claimed in claim 1 wherein measuring current information from the test structures includes measuring each of the test structures for a drain current high (Idhigh) and a drain current low (Idlow).

### Claim 3 (depends on 1)

The method as claimed in claim 1 wherein deriving the scaling factor with the currents for the stress contribution based on the active area of the circuit element in the integrated circuit includes:
calculating an effective drain current (Ideff) for each of the test structures with a drain current high (Idhigh) and a drain current low (Idlow) from each of the test structures;
providing an equation for a stress component with a distance between the active area and a stress liner of the dual stress liners;
relating a change in the effective drain current to a change of mobility in the circuit element;
relating the equation and the change to mobility for deriving the scaling factor; and further comprising:
developing a compact model for the integrated circuit with the scaling factor; and
manufacturing an electronic system with the integrated circuit manufactured with an application of the compact model.

### Claim 4 (depends on 1)

The method as claimed in claim 1 wherein measuring current information from the test structures includes measuring a drain current high (Idhigh) and a drain current low (Idlow) from a parallel test structure and an orthogonal test structure.

### Claim 5 (depends on 1)

The method as claimed in claim 1 wherein deriving the scaling factor with the currents for the stress contribution based on the active area of the circuit element in the integrated circuit includes developing a parallel proximity scaling factor (kx) and an orthogonal proximity scaling factor (ky).

### Claim 6

A method for operating an integrated circuit tester information processing system comprising:
measuring current information from test structures for an integrated circuit having dual stress liners with the test structures including parallel test structures and orthogonal test structures;
selecting a drain current high (Idhigh) and a drain current low (Idlow) for each of the test structures from the current information or stored current information;
deriving a parallel proximity scaling factor (kx1) and an orthogonal proximity scaling factor (ky) for a stress contribution based on an active area of a circuit element in the integrated circuit with the drain current high (Idhigh) and the drain current low (Idlow) for each of the test structures including:
calculating an effective drain current (Ideff) for each of the test structures with the drain current high (Idhigh) and the drain current low (Idlow),
providing an equation for a stress component with a distance between the active area and a stress liner of the dual stress liners,
relating a change in the effective drain current to a change of mobility in the circuit element, and
relating the equation and the change to mobility for deriving the scaling factor; and
correlating the stress contribution with the integrated circuit.

### Claim 7 (depends on 6)

The method as claimed in claim 6 wherein deriving the parallel proximity scaling factor (kx1) and the orthogonal proximity scaling factor (ky) for the stress contribution based on the active area includes:
deriving the parallel proximity scaling factor (kx1) with an active length of a length side of the active area and the distance between a width side to an end of the stress liner; and
deriving the orthogonal proximity scaling factor (ky) with an active width of a width side of the active area and a further distance between the length side to an adjacent end of the stress liner.

### Claim 8 (depends on 6)

The method as claimed in claim 6 wherein providing the equation for the stress component with the distance between the active area and the stress liner of the dual stress liners includes:
providing a parallal proximity stress component (σx) with the parallel proximity scaling factor (kx1); and
providing a parallal proximity stress component (σy) with the parallel proximity scaling factor (ky).

### Claim 9 (depends on 6)

The method as claimed in claim 6 wherein:
measuring the current information from the test structures includes:
measuring the current information from trench test structures; further comprising:
deriving a trench scaling factor (kx2); and
providing a parallal proximity stress component (σx) with the parallel proximity scaling factor (kx1) and the trench scaling factor (kx2).

### Claim 10 (depends on 6)

The method as claimed in claim 6 wherein correlating the stress contribution with the integrated circuit includes developing a model for estimating mobility of the integrated circuit with the parallel proximity scaling factor (kx1) and the orthogonal proximity scaling factor (ky).

### Claim 11

An integrated circuit tester information processing system comprising:
measurement circuitry for measuring current information from test structures for an integrated circuit having dual stress liners;
extraction circuitry for selecting currents from the current information or stored current information;
analysis circuitry for deriving a scaling factor with the currents for a stress contribution based on an active area of a circuit element in the integrated circuit; and
presentation circuitry for correlating the stress contribution with the integrated circuit.

### Claim 12 (depends on 11)

The system as claimed in claim 11 wherein the measurement circuitry is for measuring each of the test structures for a drain current high (Idhigh) and a drain current low (Idlow).

### Claim 13 (depends on 11)

The system as claimed in claim 11 wherein the analysis circuitry is for:
calculating an effective drain current (Ideff) for each of the test structures with a drain current high (Idhigh) and a drain current low (Idlow) from each of the test structures;
providing an equation for a stress component with a distance between the active area and a stress liner of the dual stress liners;
relating a change in the effective drain current to a change of mobility in the circuit element;
relating the equation and the change to mobility for deriving the scaling factor; and
developing a compact model for the integrated circuit with the scaling factor.

### Claim 14 (depends on 11)

The system as claimed in claim 11 wherein the measurement circuitry is for measuring a drain current high (Idhigh) and a drain current low (Idlow) from a parallel test structure and an orthogonal test structure.

### Claim 15 (depends on 11)

The system as claimed in claim 11 wherein the analysis circuitry is for developing a parallel proximity scaling factor (kx) and an orthogonal proximity scaling factor (ky).

### Claim 16 (depends on 11)

The system as claimed in claim 11 wherein:
the measurement circuitry is for measuring current information from parallel test structures and orthogonal test structures;
the extraction circuitry is for selecting a drain current high (Idhigh) and a drain current low (Idlow) for each of the test structures from the current information or stored current information;
the analysis circuitry is for deriving a parallel proximity scaling factor (kx1) and an orthogonal proximity scaling factor (ky) for a stress contribution based on the active area of a circuit element in the integrated circuit with the drain current high (Idhigh) and the drain current low (Idlow) for each of the test structures including:
calculating an effective drain current (Ideff) for each of the test structures with the drain current high (Idhigh) and the drain current low (Idlow),
providing an equation for a stress component with a distance between the active area and a stress liner of the dual stress liners,
relating a change in the effective drain current to a change of mobility in the circuit element, and
relating the equation and the change to mobility for deriving the scaling factor.

### Claim 17 (depends on 16)

The system as claimed in claim 16 wherein the analysis circuitry is for:
deriving the parallel proximity scaling factor (kx1) with an active length of a length side of the active area and the distance between the width side to an end of the stress liner; and
deriving the orthogonal proximity scaling factor (ky) with an active width of a width side of the active area and a further distance between the length side to an adjacent end of the stress liner.

### Claim 18 (depends on 16)

The system as claimed in claim 16 wherein the analysis circuitry is for:
deriving a parallal proximity stress component (σx) with the parallel proximity scaling factor (kx1); and
deriving a parallal proximity stress component (σy) with the parallel proximity scaling factor (ky).

### Claim 19 (depends on 16)

The system as claimed in claim 16 wherein:
the measurement circuitry is for:
measuring the current information from trench test structures; the analysis circuitry is for:
deriving a trench scaling factor (kx2); and
providing a parallal proximity stress component (σx) with the parallel proximity scaling factor (kx1) and the trench scaling factor (kx2).

### Claim 20 (depends on 16)

The system as claimed in claim 16 wherein the presentation circuitry is for developing a model for estimating mobility of the integrated circuit with the parallel proximity scaling factor (kx1) and the orthogonal proximity scaling factor (ky).