# US 7,610,061 B2 · Communication device and method having a common platform

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- Number: US 7,610,061 B2
- Document ID: US7610061B2
- Status: Granted
- Kind: B2
- Application number: 10/813,327
- Filed: 2004-03-30
- Published: 2005-03-24
- Granted: 2009-10-27
- Earliest claimed: 2003-09-20
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Woon-Sik Suh; Jeon Taek Im; Jin-Aeon Lee
- Web page: https://patentgrep.com/patent/US7610061B2

## CPC

- G06F 15/167: using a common memory, e.g. mailbox
- H04L 12/403: with centralised control, e.g. polling
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A communication device and method is provided, comprising: a signal modulator/demodulator having a digital signal processor for effecting radio communications; and an application processor (AP) having a central processing unit and a master controller for controlling via a common bus a plurality of peripherals including an interface with the signal modulator/demodulator, wherein a memory shared by the modem and the AP is controlled via the interface. The plurality of peripherals include at least one of an image capture module, a display, and a flash memory. The master controller controls the plurality of peripherals by issuing a packetized command commonly receivable by the plurality of peripherals over the common bus, the packetized command includes a module device select signal used for selecting one of the peripherals.

## Claims

### Claim 1

A communication device, comprising:
a signal modulator/demodulator (modem) having a digital signal processor for effecting radio communications;
a shared memory connected to the modem; and
an application processor (AP) having a central processing unit and a bus master controller for controlling via a common bus a plurality of external peripherals, the shared memory connected to the modem,
wherein the bus master controller controls the plurality of external peripherals and the shared memory by using a packet generator issuing a packet commonly receivable by the plurality of external peripherals and the shared memory over the common bus, and wherein the packet includes a module device select signal for selecting one of the plurality of external peripherals and the shared memory, and
wherein the bus master controller comprises:
a bus interface for data, address, and control signal communication with the central processing unit;
a protocol converter and protocol signal controller for receiving control signals from the central processing unit through the bus interface and managing control signal flow according to a present protocol;
an address translator for receiving the address from the central processing unit through the bus interface and translating the address depending on an application module to be accessed;
a packet generator for receiving control signals from the protocol converter and protocol signal controller and a translated address from the address translator and packetizing the control signals and the translated address in a command packet;
a receive buffer for receiving data from the central processing unit through the bus interface;
a data pack unit for arranging the received data according to a specified width of a common data structure; and
a multiplexer for receiving the command packet from the packet generator and the data packet from the data pack unit and outputting one of the command packet or the data packet to the common bus.

### Claim 2 (depends on 1)

The device of claim 1, wherein the shared memory is an SDRAM.

### Claim 3 (depends on 1)

The device of claim 1, wherein the plurality of external peripherals includes at least one of an image capture module, a display, and a flash memory.

### Claim 4 (depends on 1)

The device of claim 1, wherein the selected one of the plurality of external peripherals returns a signal to the bus master controller to acknowledge receipt of the command packet.

### Claim 5 (depends on 1)

The device of claim 1, wherein the command packet includes:
a read/write command directed to the shared memory shared by the modem and the AP.

### Claim 6 (depends on 5)

The device of claim 5, wherein data read from the shared memory is sent to the AP via a second common bus with a strobe signal, and wherein the strobe signal is used for strobing the data read into a register in a second bus master controller.

### Claim 7 (depends on 2)

The device of claim 2, wherein the SDRAM includes a plurality of data banks and an interface for interfacing a second bus master controller via a second common bus.

### Claim 8 (depends on 2)

The device of claim 2, wherein the shared memory includes a first protection circuit for receiving address data from the AP and a second protection circuit for receiving address data from the modem, each for generating a protect signal upon simultaneously receiving the same address from the modem and the AP, wherein the protect signal is generated to halt memory access by one of the modem and the AP to prevent simultaneous access of the same memory cells.

### Claim 9

A communication device, comprising:
a signal modulator/demodulator (modem) having a digital signal processor for effecting radio communications;
a shared memory connected to the modem; and
an application processor (AP) having a central processing unit, a first bus master controller connected to a plurality of external peripherals via a first common bus and a second bus master controller connected to the shared memory via a second common bus,
wherein the first bus master controller is configured for controlling via the first common bus the plurality of external peripherals,
wherein the second bus master controller is configured for controlling via the second common bus the shared memory connected to the modem,
wherein the first bus master controller controls the plurality of external peripherals operatively connected to the first common bus by issuing a packet commonly receivable by the plurality of external peripherals over the first common bus, and
wherein the packet includes a module device select signal for selecting one of the plurality of external peripherals, and
wherein the first bus master controller comprises:
a packet generator for receiving control signals and an address, and packetizing the control signals and the address in a command packet;
a data pack unit for packing data into a data packet; and
a multiplexer for receiving the command packet from the packet generator and the data packet from the data pack unit and outputting one of the command packet or the data packet to the common bus;
a protocol converter and protocol signal controller for receiving second control signals from the central processing unit through the bus interface and managing control signal flow according to a present protocol;
an address translator for receiving a second address from the central processing unit through the bus interface and translating the second address into the address depending on an application module to be accessed; and
a receive buffer for receiving the data from the central processing unit through the bus interface.

### Claim 10 (depends on 9)

The device of claim 9, wherein at least one peripheral of the plurality of external peripherals is an image capture module.

### Claim 11 (depends on 9)

The device of claim 9, wherein the selected one of the plurality of peripherals returns a signal over the first common bus to the first bus master controller in the AP to acknowledge receipt of the packetized command.

### Claim 12 (depends on 9)

The device of claim 9, wherein data read from the shared memory is transmitted via the second common bus to the second bus master controller in the AP with a strobe signal, and wherein the strobe signal is for strobing the data read into a register in the second bus master controller.

### Claim 13 (depends on 9)

The device of claim 9, wherein the shared memory is an SDRAM.

### Claim 14 (depends on 13)

The device of claim 13, wherein the SDRAM includes a plurality of data banks and an interface for interfacing.

### Claim 15 (depends on 13)

The device of claim 13, wherein
the SDRAM includes a first protection circuit for receiving address data from the AP and a second protection circuit for receiving address data from the modem and for generating a protect signal upon simultaneously receiving the same address from the modem and the AP.

### Claim 16

An application processor (AP), for use in a communication device, comprising:
a central processing unit for processing data received from a plurality of external peripherals and from a shared memory; and
a bus master controller for controlling via a common bus the plurality of external peripherals and the shared memory; and
wherein the shared memory is connected to a signal modulator/demodulator (modem),
wherein the bus master controller controls the plurality of peripherals and the shared memory by issuing a packet commonly receivable by the plurality of external peripherals and the shared memory over the common bus, and
wherein the packet includes a module device select signal used for selecting one of the plurality of external peripherals and the shared memory
wherein the bus master controller comprises:
a bus interface for data, address, and control signal communication with the central processing unit;
a protocol converter and protocol signal controller for receiving control signals from the central processing unit through the bus interface and managing control signal flow according to a present protocol;
an address translator for receiving the address from the central processing unit through the bus interface and translating the address depending on an application module to be accessed;
a packet generator for receiving control signals from the protocol converter and protocol signal controller and a translated address from the address translator and packetizing the control signals and the translated address in a command packet;
a receive buffer for receiving data from the central processing unit through the bus interface;
a data pack unit for arranging the received data according to a specified width of a common data structure; and
a multiplexer for receiving the command packet from the packet generator and the data packet from the data pack unit and outputting one of the command packet or the data packet to the common bus.

### Claim 17 (depends on 16)

The device of claim 16, wherein the shared memory is an SDRAM.

### Claim 18 (depends on 16)

The device of claim 16, wherein the plurality of external peripherals additionally includes at least one of an image capture module, a display, and a flash memory.

### Claim 19 (depends on 16)

The device of claim 16, wherein the selected one of the plurality of external peripherals returns a signal to the bus master controller over the common bus to acknowledge receipt of the command packet.

### Claim 20 (depends on 16)

The device of claim 16, wherein the data read from the shared memory is sent over a second common bus to the AP with a strobe signal, and wherein the strobe signal is used for strobing the read data into a register of a second bus master controller.

### Claim 21 (depends on 17)

The device of claim 17, wherein the SDRAM includes a plurality of data banks and an interface for interfacing a second bus master controller.

### Claim 22 (depends on 17)

The device of claim 17, wherein the SDRAM includes a first protection circuit for receiving address data from the AP over a second common bus and a second protection circuit for receiving address data from the modem and for generating a protect signal upon simultaneous receipt of the same address from the AP and the modem.

### Claim 23

An application processor (AP) for use in a communication device comprising:
a central processing unit for processing data received from a plurality of external peripherals over a first common bus and from a shared memory over a second common bus; and
a first bus master controller for controlling via the first common bus the plurality of external peripherals; and
a second bus master controller for interfacing via the second common bus with the shared memory that is connected to a signal modulator/demodulator (modem),
wherein the first bus master controller controls the plurality of external peripherals by issuing a packet commonly receivable by the plurality of external peripherals over the first common bus, and
wherein the packet includes a module device select signal for selecting one of the plurality of external peripherals, and
wherein the first bus master controller comprises:
a bus interface for data, address, and control signal communication with the central processing unit;
a protocol converter and protocol signal controller for receiving control signals from the central processing unit through the bus interface and managing control signal flow according to a present protocol;
an address translator for receiving the address from the central processing unit through the bus interface and translating the address depending on an application module to be accessed;
a packet generator for receiving control signals from the protocol converter and protocol signal controller and a translated address from the address translator and packetizing the control signals and the translated address in a command packet;
a receive buffer for receiving data from the central processing unit through the bus interface;
a data pack unit for arranging the received data according to a specified width of a common data structure; and
a multiplexer for receiving the command packet from the packet generator and the data packet from the data pack unit and outputting one of the command packet or the data packet to the common bus.

### Claim 24 (depends on 23)

The device of claim 23, wherein the shared memory is an SDRAM.

### Claim 25 (depends on 23)

The device of claim 23, wherein the plurality of external peripherals includes at least one of an image capture module, a display, and a flash memory.

### Claim 26 (depends on 23)

The device of claim 23, wherein the selected one of the peripherals returns a signal over the first common bus to the first bus master controller to acknowledge receipt of the command packet.

### Claim 27 (depends on 23)

The device of claim 23, wherein the data read from the shared memory is sent to the AP over the second common bus with a strobe signal, and wherein the strobe signal is used for strobing the data read into a register in the second bus master controller.

### Claim 28 (depends on 24)

The device of claim 24, wherein the SDRAM includes a plurality of data banks and an interface for interfacing with the second bus master controller over the second common bus.

### Claim 29

A method of controlling a communication device having a signal modulator/demodulator (modem) for effecting radio communications, an application processor (AP) having a central processing unit, a bus master controller and a shared memory, the method comprising:
controlling via a common bus a plurality of external peripherals using the bus master controller; and
interfacing with the modem via the shared memory and the common bus using the bus master controller,
wherein the step of controlling the plurality of external peripherals includes:
receiving control signals from the central processing unit and managing control signal flow according to a present protocol, by using a protocol converter and protocol signal controller;
receiving an address from the central processing unit and translating the address depending on the external peripheral to be accessed, by using an address translator;
receiving control signals from the protocol converter and protocol signal controller and a translated address from the address translator and packetizing the control signals and the translated address in a command packet, by using a packet generator;
receiving data from the central processing unit by using a receive buffer;
arranging the received data according to a specified width of a common data structure, by using a data pack unit; and
receiving the command packet from the packet generator and the data packet from the data pack unit and outputting one of the command packet or the data packet to the common bus, by using a multiplexer.

### Claim 30 (depends on 29)

The method of claim 29, wherein the shared memory is an SDRAM.

### Claim 31 (depends on 29)

The method of claim 29, wherein the step of controlling includes controlling at least one of an image capture module, a display, and a flash memory included in the plurality of external peripherals.

### Claim 32 (depends on 29)

The method of claim 29, wherein the selected one of the plurality of external peripherals returns a signal to the bus master controller over the common bus to acknowledge receipt of the command packet.

### Claim 33 (depends on 29)

The method of claim 29, wherein data read from the shared memory is transmitted over a second common bus to the AP with a strobe signal, and wherein the strobe signal is for strobing the data read into a register in a second bus master controller.

### Claim 34 (depends on 29)

The method of claim 29, further including receiving address data from the AP over a second common bus and from the modem at the shared memory and generating a protect signal upon simultaneously receiving the same address from the modem and the AP.