# US 7,609,801 B2 · Counter circuit and method of operating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,609,801 B2 - Document ID: US7609801B2 - Status: Granted - Kind: B2 - Application number: 11/819,863 - Filed: 2007-06-29 - Published: 2008-02-14 - Granted: 2009-10-27 - Earliest claimed: 2006-08-11 - Assignees: Hynix Semiconductor Inc. - Inventors: Jae-Boum Park; Young-Bo Shim - Web page: https://patentgrep.com/patent/US7609801B2 ## CPC - H03K 23/548: {Reversible counters} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A control unit that outputs a plurality of control signals in response to the input of a plurality of counter enable signals allocated into the numerical value of a multiple of 2 is provided. An operating unit increments or decrements by a multiple of 2 in response to input of the plurality of control signals and count up-down signals. ## Claims ### Claim 1 A counter circuit, comprising: a control unit that outputs a plurality of control signals in response to input of a plurality of counter enable signals; and an operating unit that increments or decrements by 2 or more in response to the plurality of control signals and to count up-down signals, wherein the control unit includes; a first multiplexing unit configured to generate a first control signal using the counter enable signals by numeric values 1 and 2, a second multiplexing unit configured to generate a second control signal using the counter enable signals by numeric values 2 and 4, a third multiplexing unit configured to generate a first control signal using the counter enable signals by numeric values 4 and 8, and a fourth multiplexing unit configured to generate a first control signal using the counter enable signals by numeric values 8 and 1. ### Claim 2 (depends on 1) The counter circuit of claim 1, wherein during the counting up or down operation by 1, the first control signal that controls the counting up or down operation with respect to a last digit among the plurality of control signals is enabled, during the counting up or down operation by 2, the first control signal is disabled and the second control signal that controls the counting up or down operation with respect to a digit before the last digit among the plurality of control signals is enabled, during the counting up or down operation by 4, the first and second control signals are disabled, and the third control signal that controls the counting up or down operation with respect to a second digit from the last digit among the plurality of control signals is enabled, and during the counting up or down operation by 8, the first to third control signals are disabled, and the fourth control signal that controls the counting up or down operation with respect to a third digit from the last digit among the plurality of control signals is enabled. ### Claim 3 (depends on 2) The counter circuit of claim 2, wherein when the control signal of a corresponding digit is disabled, the operating unit performs the counting up or down operation by 1 with respect to data of the digit corresponding to the control signal that is enable to the first digit before the digit corresponding to the control signal that is enabled, without changing the data of the digit corresponding to the control signal that is enabled. ### Claim 4 (depends on 2) The counter circuit of claim 2, wherein the first multiplexing unit includes a first multiplexer that includes a first input terminal to which the counter enable signal by the numerical value of 1 is input, a second input terminal connected to a ground terminal, and a control terminal to which the counter enable signal by the numerical value of 2 is input and that outputs the first control signal in response to the counter enable signal by the numerical value of 2, wherein the second multiplexing unit includes a second multiplexer and a third multiplexer, the second multiplexer includes a first input terminal to which the counter enable signal by the numerical value of 1 is input, a second input terminal connected to the ground terminal, and a control terminal to which the counter enable signal by the numerical value of 4 is input, and outputs a signal in response to the counter enable signal by the numerical value of 4; the third multiplexer includes a first input terminal to which a carry of the last digit is input, a second input terminal to which the signal output of the second multiplexer is input, and a control terminal to which the counter enable signal by the numerical value of 2 is input, and outputs the second control signal in response to the counter enable signal by the numerical value of 2, wherein the third multiplexing unit including a fourth multiplexer and a fifth multiplexer, the fourth multiplexer includes a first input terminal to which the counter enable signal by the numerical value of 1 is input, a second input terminal connected to the ground terminal, and a control terminal to which the counter enable signal by the numerical value of 8 is input, and outputs a signal in response to the counter enable signal by the numerical value of 8; the fifth multiplexer includes a first input terminal to which a carry of the digit before the last digit is input, a second input terminal to which the signal output of the fourth multiplexer is input, and the control terminal to which a counter enable signal by the numerical value of 4 is input, and outputs the third control signal in response to the counter enable signal by the numerical value of 4, and wherein the fourth multiplexing unit includes a sixth multiplexer that includes a first input terminal to which a carry of the second digit from the last digit is input, a second input terminal to which the counter enable signal by the numerical value of 1, and a control terminal to which the counter enable signal by the numerical value of 8 is input, and that outputs the fourth control signal in response to the counter enable signal by the numerical value of 8. ### Claim 5 (depends on 4) The counter circuit of claim 4, wherein each of the first to sixth multiplexers selectively outputs the signal input to its respective first or second input terminal, on the basis of the input to the control terminal. ### Claim 6 (depends on 3) The counter circuit of claim 3, wherein the operating unit further includes first to fourth flip-flops each of which receives a clock signal, a reset signal, and one of the first to fourth control signals to perform the counting up or down operation with respect to one digit indicated by the count up-down signal, and outputs a result of the counting up or down operation to a data output terminal or a carry output terminal.