# US 7,609,800 B1 · Counter of semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,609,800 B1 - Document ID: US7609800B1 - Status: Granted - Kind: B1 - Application number: 12/163,910 - Filed: 2008-06-27 - Published: 2009-11-19 - Granted: 2009-10-27 - Earliest claimed: 2008-05-13 - Assignees: Hynix Semiconductor Inc. - Inventors: Sang Oh Lim; Byoung Kwan Jeong; Mi Sun Yoon - Web page: https://patentgrep.com/patent/US7609800B1 ## CPC - H03K 23/40: Gating or clocking signals applied to all stages, i.e. synchronous counters {(H03K23/74 - H03K23/84 take precedence)} - H03K 23/50: using bi-stable regenerative trigger circuits (H03K23/42 - H03K23/48 take precedence) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract The present invention relates to a unit counter block. According to an aspect of the present invention, the unit counter block includes a D-flipflop, a second MUX, and a first MUX. The-flipflop outputs first and second output signals in synchronism with a clock signal. The second MUX selects any one of external data and the second output signal of the D-flipflop in response to a data load signal and outputs a selected signal. The first MUX transfers any one of the first output signal of the D-flipflop and the output signal of the second MUX as an input signal of the D-flipflop in response to a counter enable signal or the data load signal. ## Claims ### Claim 1 A unit counter block, comprising: a D-flipflop that outputs first and second output signals according to a clock signal; a second selector to select one from external data and the second output signal of the D-flipflop in response to a data load signal and output a selected signal; and a first selector to transfer one from the first output signal of the D-flipflop and the output signal of the second selector as an input signal of the D-flipflop in response to a counter enable signal or the data load signal. ### Claim 2 (depends on 1) The unit counter block of claim 1, wherein the D-flipflop outputs an input signal from a point of time at which a first rising edge of the clock signal is input to a point of time at which a second rising edge of the clock signal is input as the first output signal, wherein the first and second selectors are multiplexers. ### Claim 3 (depends on 1) The unit counter block of claim 1, wherein the first selector transfers the output signal of the second selector as the input signal of the D-flipflop when the counter enable signal of a high level is applied, and transfers the first output signal of the D-flipflop as the input signal of the D-flipflop when the counter enable signal of a low level is applied. ### Claim 4 (depends on 1) The unit counter block of claim 1, wherein the second selector transfers the external data to the first selector when a data input signal of a high level is input, and transfers the second output signal of the D-flipflop to the first selector when the data input signal of a low level is input. ### Claim 5 (depends on 1) The unit counter block of claim 1, wherein the first selector transfers the external data, which is transferred from the second selector, as the input signal of the D-flipflop when a data input signal of a high level is input. ### Claim 6 (depends on 1) The unit counter block of claim 1, wherein the unit counter block outputs the first output signal that is toggled at a cycle being twice that of the clock signal when the counter enable signal of a high level is input, and outputs the first output signal that is held at a specific level when the counter enable signal of a low level is input. ### Claim 7 (depends on 1) The unit counter block of claim 1, further comprising an output unit for inverting the second output signal of the D-flipflop and outputting an inverted output. ### Claim 8 (depends on 1) The unit counter block of claim 1, further comprising a selector control unit to control an operation of the first selector using a logically summed signal of the counter enable signal and the data load signal. ### Claim 9 A 2-bit counter, comprising: a first unit counter block, comprising a D-flipflop, a second selector to select one from external data and a second output signal of the D-flipflop in response to a data load signal and output a selected signal, and a first selector to transfer one from a first output signal of the D-flipflop and the output signal of the second selector as an input signal of the D-flipflop in response to a counter enable signal or the data load signal; and a second unit counter block, comprising a D-flipflop, a second selector to select one from external data and a second output signal of the D-flipflop in response to a data load signal and output a selected signal, and a first selector to transfer one from a first output signal of the D-flipflop and the output signal of the second selector as an input signal of the D-flipflop in response to the output signal of the second selector of the first counter block and a counter enable signal or the data load signal. ### Claim 10 (depends on 9) The 2-bit counter of claim 9, wherein: the first output signal of the D-flipflop included in the first counter block is used as a first bit signal, and the first output signal of the D-flipflop included in the second counter block is used as a second bit signal. ### Claim 11 (depends on 9) The 2-bit counter of claim 9, wherein each of the first and second counter blocks further comprises an output unit to invert the second output signal of the D-flipflop and output an inverted signal. ### Claim 12 (depends on 9) The 2-bit counter of claim 9, wherein: the first output signal of the D-flipflop included in the first counter block is a signal that is toggled at a cycle being twice that of a clock signal applied to the D-flipflop, and the first output signal of the D-flipflop included in the second counter block is a signal that is toggled at a cycle being twice that of the first output signal of the D-flipflop included in the first counter block. ### Claim 13 (depends on 9) The 2-bit counter of claim 9, wherein: during a period where the output signal of the second selector of the first counter block is held at a low level, the first output signal of the D-flipflop of the second counter block is toggled, and during a period where the output signal of the second selector of the first counter block is held at a high level, the first output signal of the D-flipflop of the second counter block is held. ### Claim 14 (depends on 9) The 2-bit counter of claim 9, wherein the first selector of the first counter block transfers the output signal of the second selector of the first counter block as the input signal of the D-flipflop of the first counter block when the counter enable signal of a high level is input, and transfers the first output signal of the D-flipflop as the input signal of the D-flipflop of the first counter block when the counter enable signal of a low level is input. ### Claim 15 (depends on 9) The 2-bit counter of claim 9, wherein the first selector of the second counter block transfers the output signal of the second selector of the second counter block as the input signal of the D-flipflop of the second counter block when the output signal of the second selector of the first counter block is at a low level and the counter enable signal of the first counter block is at a high level, and transfers the first output signal of the D-flipflop as the input signal of the D-flipflop when the output signal of the second selector of the first counter block is at a high level or the counter enable signal of the first counter block is at a low level. ### Claim 16 (depends on 9) The 2-bit counter of claim 9, wherein the second selector of each of the first and second counter blocks transfers the external data to the first selector when a data input signal of a high level is input and transfers the second output signal of the D-flipflop to the first selector when the data input signal of a low level is input. ### Claim 17 (depends on 9) The 2-bit counter of claim 9, wherein the first selector of each of the first and second counter blocks transfers the external data that is transferred from the second selector as the input signal of the D-flipflop when a data input signal of a high level is input. ### Claim 18 (depends on 9) The 2-bit counter of claim 9, wherein the second counter block further comprises a selector control unit, comprising an inverter to invert the output signal of the second selector of the first counter block, a AND gate to perform a AND operation on an output signal of the inverter and the counter enable signal, and a OR gate for performing a OR operation on an output signal of the AND gate and the data load signal. ### Claim 19 An n-bit counter, comprising n counter blocks respectively comprising a D-flipflop, a second selectors to select one from external data and a second output signal of the D-flipflop in response to a data load signal and output a selected signal, and a first selector to transfer one from a first output signal of the D-flipflop and the output signal of the second selector as an input signal of the D-flipflop in response to a counter enable signal or the data load signal, wherein an mth counter block outputs an mth bit signal that is toggled in a period where all output signals of the second selectors included in first to (m−1)th counter blocks are at a first level and the counter enable signal is at a second level. ### Claim 20 (depends on 19) The n-bit counter of claim 19, wherein the mth bit signal is a signal that is toggled at a cycle being twice that of a (m−1)th bit signal output from the (m−1)th counter block. ### Claim 21 (depends on 19) The n-bit counter of claim 19, wherein the mth counter block further comprises a selector control unit, comprising a OR gate to perform a OR operation on output signals of second selectors included in the first to (m−1)th counter blocks, a AND gate to perform a NAND operation on an output signal of the NOR gate and the counter enable signal, and a OR gate to perform a NOR operation on an output signal of the AND gate and the data load signal. ### Claim 22 (depends on 19) The n-bit counter of claim 19, wherein the mth counter block outputs the mth bit signal that is held in a period where any one of the output signals of the second selectors included in the first to (m−1)th counter blocks is at the second level or the counter enable signal is at the first level.