# US 7,609,798 B2 · Calibrating a phase detector and analog-to-digital converter offset and gain

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- Number: US 7,609,798 B2
- Document ID: US7609798B2
- Status: Granted
- Kind: B2
- Application number: 11/026,206
- Filed: 2004-12-29
- Published: 2006-06-29
- Granted: 2009-10-27
- Earliest claimed: 2004-12-29
- Assignees: Silicon Laboratories Inc.
- Inventors: Adam B. Eldredge; Jeffrey S. Batchelor; Gary Hammes
- Web page: https://patentgrep.com/patent/US7609798B2

## CPC

- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L 7/0004: {Initialisation of the receiver (H04L7/0075 and H04L7/10 take precedence)}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

The present invention includes apparatus and methods to calibrate a phase detector and an analog-to-digital converter (ADC) offset and gain. In one such embodiment, an apparatus includes a phase detector to generate an error pulse and a reference pulse, a combiner to combine the pulses, and an ADC to receive the combined pulses, where the ADC has a full scale set by an average of the reference pulse. Still further, a calibration loop may be coupled between the output of the ADC and the phase detector to generate and provide a phase adjust signal to reduce or eliminate phase offsets. Other embodiments are described and claimed.

## Claims

### Claim 1

An apparatus comprising:
a phase detector to generate an error pulse and a reference pulse;
a combiner to combine the error pulse and the reference pulse into a phase detector pulse; and
an analog-to-digital converter (ADC) coupled to receive the phase detector pulse, the ADC having a full scale set by an average of the reference pulse.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the ADC comprises a sigma-delta converter.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the sigma-delta converter comprises a feedback loop to feedback either a positive or negative full scale signal to combine with the phase detector pulse.

### Claim 4 (depends on 1)

The apparatus of claim 1, further comprising a digital filter coupled to receive an output of the ADC.

### Claim 5 (depends on 1)

The apparatus of claim 1, further comprising a low-pass filter coupled between the phase detector and the ADC, the low-pass filter to generate the average of the reference pulse.

### Claim 6 (depends on 2)

The apparatus of claim 2, wherein a gain of the phase detector and ADC is dependent on current matching between a current of the full scale signal and a current of the reference pulse.

### Claim 7

An apparatus comprising:
a phase detector to generate a phase detector pulse;
an analog-to-digital converter (ADC) coupled to receive the phase detector pulse;
a calibration loop coupled to receive an output of the ADC and to generate a phase adjust value to force an average value of the ADC output to be substantially zero; and
storage to store the phase adjust value.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the calibration loop comprises:
a filter to receive the ADC output; and
an inverting gain stage coupled to an output of the filter.

### Claim 9 (depends on 7)

The apparatus of claim 7, wherein the phase detector comprises a multiplier to combine the phase adjust value with an error pulse or a reference pulse.

### Claim 10 (depends on 7)

The apparatus of claim 7, wherein the phase detector to receive a sampling clock having a phase continuously swept across a data eye during calibration.

### Claim 11 (depends on 7)

The apparatus of claim 7, further comprising a multiplexer coupled to the phase detector to provide incoming data or an asynchronous clock to the phase detector.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the multiplexer to provide the asynchronous clock to the phase detector if the incoming data has less than a predetermined amount of transitions.

### Claim 13 (depends on 7)

The apparatus of claim 7, wherein the phase detector comprises:
a first latch to receive incoming data and having a first delay; and
a delay element to receive the incoming data, the delay element unmatched to the first delay.

### Claim 14

A system comprising:
an amplifier to receive optical energy and convert the optical energy to electrical energy;
a phase detector coupled to the amplifier to generate a phase detector pulse, and to develop an error pulse and a reference pulse to combine into the phase detector pulse;
an analog-to-digital converter (ADC) coupled to receive the phase detector pulse; and
a calibration loop coupled to receive an output of the ADC and to generate a phase adjust value to force a filtered value of the ADC output to be substantially zero.

### Claim 15 (depends on 14)

The system of claim 14, wherein the ADC has a full scale set by an average of the reference pulse.

### Claim 16 (depends on 14)

The system of claim 14, further comprising a low-pass filter coupled between the phase detector and the ADC, the low-pass filter to generate an average of the reference pulse.

### Claim 17 (depends on 15)

The system of claim 15, wherein a gain of the phase detector and ADC is dependent on current matching between a current of the full scale and a current of the reference pulse.

### Claim 18 (depends on 14)

The system of claim 14, wherein the phase detector comprises:
a first latch to receive incoming data and having a first delay; and
a delay element to receive the incoming data, the delay element unmatched to the first delay.

### Claim 19 (depends on 14)

The system of claim 14, further comprising a transition detector to detect an amount of data transitions during a calibration phase.

### Claim 20 (depends on 19)

The system of claim 19, further comprising a multiplexer to receive a control signal from the transition detector and to select incoming data or a transition simulator for input into the phase detector.

### Claim 21

An apparatus comprising:
a phase detector to receive incoming data and to output the incoming data and a phase detector pulse, and including a multiplier to combine a phase adjust value with an error pulse;
an analog-to-digital converter (ADC) coupled to receive the phase detector pulse; and
a calibration circuit coupled to receive an output of the ADC and to generate the phase adjust value to force an average value of the ADC output to be substantially zero.

### Claim 22 (depends on 21)

The apparatus of claim 21, wherein the calibration circuit comprises:
a filter to receive the ADC output; and
an inverting gain stage coupled to an output of the filter.

### Claim 23 (depends on 21)

The apparatus of claim 21, wherein the calibration circuit is closed during calibration.

### Claim 24 (depends on 21)

The apparatus of claim 21, further comprising storage to store the phase adjust value.

### Claim 25 (depends on 21)

The apparatus of claim 21, wherein the phase detector is to receive a sampling clock having a phase continuously swept across a data eye during calibration.

### Claim 26 (depends on 21)

The apparatus of claim 21, further comprising a multiplexer coupled to the phase detector to provide the incoming data or an asynchronous clock to the phase detector.

### Claim 27 (depends on 26)

The apparatus of claim 26, wherein the multiplexer is to provide the asynchronous clock to the phase detector if the incoming data has less than a predetermined amount of transitions.