# US 7,609,758 B2 · Method of phase shifting bits in a digital signal pattern

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- Number: US 7,609,758 B2
- Document ID: US7609758B2
- Status: Granted
- Kind: B2
- Application number: 10/836,178
- Filed: 2004-04-30
- Published: 2005-11-03
- Granted: 2009-10-27
- Earliest claimed: 2004-04-30
- Assignees: Agilent Technologies, Inc.
- Inventors: Roger L. Jungerman
- Web page: https://patentgrep.com/patent/US7609758B2

## CPC

- H04L 1/205: {jitter monitoring}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A method of phase shifting bits in a digital signal pattern combines a bit-wise phase-shift signal with an external clock signal to produce a perturbed clock signal. The perturbed clock signal is provided to a digital pattern source to generate a shifted digital signal pattern wherein at least one bit is selectively phase-shifted according to the bit-wise phase-shift signal.

## Claims

### Claim 1

A method of phase shifting bits in a digital signal pattern comprising:
applying a bit-wise phase-shift signal to a clock signal to produce a perturbed clock signal;
providing the perturbed clock signal to a digital pattern source; and
generating a shifted digital signal pattern wherein at least one bit is selectively phase-shifted according to the bit-wise phase-shift signal;
wherein the bit-wise phase-shift signal comprises a sum of a plurality of digital signals from a plurality of digital pattern generators, the plurality of digital signals are combined in a binary ladder.

### Claim 2 (depends on 1)

The method of claim 1 wherein the plurality of digital pattern generators
and the digital pattern source form at least a portion of an integrated circuit.

### Claim 3 (depends on 2)

The method of claim 2 wherein the integrated circuit comprises an application-specific integrated circuit.

### Claim 4 (depends on 2)

The method of claim 2 wherein the integrated circuit comprises a programmable logic device.

### Claim 5

A method of phase shifting bits in a digital signal pattern comprising:
applying a bit-wise phase-shift signal to a clock signal to produce a perturbed clock signal;
providing the perturbed clock signal to a digital pattern source; and
generating a shifted digital signal pattern wherein at least one bit is selectively phase-shifted according to the bit-wise phase-shift signal;
wherein the bit-wise phase-shift signal comprises a sum of a plurality of digital signals from a plurality of digital pattern generators;
wherein the plurality of digital signals are combined in a binary ladder; and
wherein the plurality of digital pattern generators comprises bit error ratio tester modules.

### Claim 6 (depends on 5)

The method of claim 5 wherein the digital pattern source comprises a bit error ratio tester module.

### Claim 7 (depends on 5)

The method of claim 5 wherein the bit error ratio tester modules are part of a parallel bit error ratio tester and the digital pattern source comprises a bit error ratio tester module in the parallel bit error ratio tester.

### Claim 8

A method of phase shifting bits in a digital signal pattern comprising:
applying a bit-wise phase-shift signal to a clock signal to produce a perturbed clock signal;
providing the perturbed clock signal to a digital pattern source; and
generating a shifted digital signal pattern wherein at least one bit is selectively phase-shifted according to the bit-wise phase-shift signal;
wherein the step of applying the bit-wise phase-shift signal to the clock signal comprises adding the bit-wise phase-shift signal to the clock signal in a resistive combiner.

### Claim 9

A method of phase shifting bits in a digital signal pattern comprising:
applying a bit-wise phase-shift signal to a clock signal to produce a perturbed clock signal;
providing the perturbed clock signal to a digital pattern source; and
generating a shifted digital signal pattern wherein at least one bit is selectively phase-shifted according to the bit-wise phase-shift signal;
wherein the step of applying the bit-wise phase-shift signal to the clock signal comprises providing the clock signal to a quadrature hybrid coupler, attenuating at least a first output of the quadrature hybrid coupler according to the bit-wise phase-shift signal, and adding the first output of the quadrature hybrid coupler to a second output of the quadrature hybrid coupler.

### Claim 10

A method of phase shifting bits in a digital signal pattern comprising:
applying a bit-wise phase-shift signal to a clock signal to produce a perturbed clock signal;
providing the perturbed clock signal to a digital pattern source; and
generating a shifted digital signal pattern wherein at least one bit is selectively phase-shifted according to the bit-wise phase-shift signal; and further comprising steps, prior to the step of applying the bit-wise phase-shift signal, of:
measuring data-dependent jitter of the digital signal pattern;
determining a worst-case data dependent jitter transition; and
selecting a digital level sufficient to correct the worst-case data-dependent jitter transition.

### Claim 11 (depends on 10)

The method of claim 10 further comprising the step of:
programming a jitter reference source to generate the digital level in the bit-wise phase-shift signal.

### Claim 12 (depends on 11)

The method of claim 11 further comprising steps, after the step of
calculating a digital level, of:
calculating digital signal levels sufficient to compensate a plurality of data-dependent jitter transitions in the digital signal pattern;
generating the bit-wise phase-shift signal to compensate the plurality of data-dependent jitter transitions in the shifted digital signal pattern.

### Claim 13 (depends on 12)

The method of claim 12 wherein the step of generating the bit-wise phase-shift signal comprises sub-sets of:
generating a plurality of digital signals from a plurality of synchronized digital pattern generators; and
combining the plurality of digital signals.

### Claim 14 (depends on 13)

The method of claim 13 wherein in a digital pattern generator of the plurality of synchronized digital pattern generators provides a voltage level different from each of a remainder of the plurality of digital pattern generators.

### Claim 15

A method of phase shifting bits in a digital signal pattern comprising:
applying a bit-wise phase-shift signal to a clock signal to produce a perturbed clock signal;
providing the perturbed clock signal to a digital pattern source; and
generating a shifted digital signal pattern wherein at least one bit is selectively phase-shifted according to the bit-wise phase-shift signal;
further comprising steps, prior to the step of combining the bit-wise phase-shift signal, of: measuring data-dependent jitter of the digital signal pattern;
determining a worst-case data dependent jitter transition; and
selecting a digital level sufficient to correct the worst-case data-dependent jitter transition;
further comprising the step of:
programming a jitter reference source to generate the digital level in the bit-wise phase-shift signal and further comprising steps, after the step of calculating a digital level, of:
calculating digital signal levels sufficient to compensate a plurality of data-dependent jitter transitions in the digital signal pattern;
generating the bit-wise phase-shift signal to compensate the plurality of data-dependent jitter transitions in the shifted digital signal pattern,
wherein a digital pattern generator of the plurality of synchronized digital pattern generators provides a voltage level different from each of a remainder of the plurality of digital pattern generators; and
wherein a first digital pattern generator produces a first voltage level and a second digital pattern generator produces a second voltage level, the first voltage level being 2n times the second voltage level, where n is an integer.