# US 7,609,723 B2 · Packet combining on PCI express

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- Number: US 7,609,723 B2
- Document ID: US7609723B2
- Status: Granted
- Kind: B2
- Application number: 10/444,164
- Filed: 2003-05-23
- Published: 2004-11-25
- Granted: 2009-10-27
- Earliest claimed: 2003-05-23
- Assignees: Intel Corporation
- Inventors: Peter R. Munguia
- Web page: https://patentgrep.com/patent/US7609723B2

## CPC

- H04L 12/4633: {Interconnection of networks using encapsulation techniques, e.g. tunneling}
- H04L 2212/00: Encapsulation of packets
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A method and device for combining packets is disclosed. In various embodiments, a plurality of packets that are compliant with a particular protocol are combined into a single packet of the same protocol. The single packet also preserves identification information for each of the combined packets within the single packet. The identification information can be used to partition and/or route the combined packets to their respective destinations.

## Claims

### Claim 1

A method comprising:
combining a plurality of packets that are compliant with a local computer-bus interconnect protocol into a single packet that is compliant with the same protocol;
preserving identification information for each of the combined packets within the single packet;
adding an indication to the single packet to indicate that the combined packets are contained within the single packet, wherein combining is performed during at least one of a time (i) prior to resynchronization of a Peripheral Component Interconnect (“PCI”) Express link, and (ii) during resynchronization of a PCI Express link;
increasing efficiency of sending data in the plurality of packets or increasing the port utilization of a port used to send the plurality of packets; and
delaying resynchronization by a PCI Express device of a PCI Express link based on at least one of a fixed amount of time and satisfying a minimum combined packet size threshold required for transmission on the link.

### Claim 2 (depends on 1)

The method of claim 1, wherein adding comprises:
attaching a header to the single packet.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
sending the single packet to a device capable of combining and partitioning packets;
saving power required to send the plurality of packets; and
reducing stuffing involved to send the plurality of packets according to the protocol.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
receiving the single packet; and
sending the single packet to another device.

### Claim 5 (depends on 3)

The method of claim 3, further comprising:
receiving the single packet; and
extracting the combined packets.

### Claim 6 (depends on 5)

The method of claim 5, further comprising:
sending each extracted packet to an appropriate destination.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
saving power of the link by intentionally performing the delaying.

### Claim 8

An apparatus comprising:
a first Peripheral Component Interconnect (“PCI”) Express device
combining a plurality of packets that are compliant with PCI Express into a single packet that is compliant with PCI Express, the single packet to contain identification information for each of the combined packets within the single packet and a header to indicate that the combined packets are contained within the single packet,
sending the single packet over a PCI Express link; and
intentionally delaying resynchronization of the link by delaying sending the single packet to save line power;
reducing stuffing required to send the plurality of packets over the link; and
a second PCI Express device to receive the single packet.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the first PCI Express device comprises one of a PCI Express root device, a PCI Express switch device, and a PCI Express peripheral device, and the second PCI Express device comprises one of a PCI Express root device, a PCI Express switch device, and a PCI Express peripheral device.

### Claim 10 (depends on 8)

The apparatus of claim 8, wherein the second PCI Express device is capable of at least one of (i) routing the single packet to another PCI Express device, (ii) extracting the combined packets from the single packet, and (iii) sending the extracted packets to a destination determined by a header of each extracted packet.

### Claim 11

A system comprising:
a graphics controller;
a first Peripheral Component Interconnect (“PCI”) Express device coupled to the graphics controller, the first PCI Express device
combining a plurality of packets that are compliant with PCI Express into a single packet that is compliant with PCI Express, the single packet to contain identification information for each of the combined packets within the single packet and a header to indicate that the combined packets are contained within the single packet,
sending the single packet over a PCI Express link; and
intentionally delaying resynchronization of the link by delaying sending the single packet to save line power;
reducing stuffing required to send the plurality of packets over the link; and
a second PCI Express device to receive the single packet.

### Claim 12 (depends on 11)

The system of claim 11, wherein the first PCI Express device comprises one of a PCI Express root device, a PCI Express switch device, and a PCI Express peripheral device, and the second PCI Express device comprises one of a PCI Express root device, a PCI Express switch device, and a PCI Express peripheral device.

### Claim 13 (depends on 11)

The system of claim 11, wherein the second PCI Express device is capable of at least one of (i) routing the single packet to another PCI Express device, (ii) extracting the combined packets from the single packet, and (iii) sending the extracted packets to a destination determined by a header of each extracted packet.

### Claim 14

A machine-readable medium containing instructions that, when executed by a machine, cause the machine to perform operations comprising:
combining a plurality of packets that are compliant with a local computer-bus interconnect protocol into a single packet that is compliant with the same protocol;
preserving identification information for each of the combined packets within the single packet;
adding an indication to the single packet to indicate that the combined packets are contained within the single packet;
delaying resynchronization of a Peripheral Component Interconnect Express link based on at least one of a fixed amount of time and satisfying a minimum combined packet size threshold required for transmission on the link; and
saving power of the link by intentionally performing the delaying.

### Claim 15 (depends on 14)

The machine-readable medium of claim 14, wherein adding an indication comprises:
attaching a header to the single packet.

### Claim 16 (depends on 14)

The machine-readable medium of claim 14, wherein the operations further comprise:
sending the single packet to a device capable of combining and partitioning packets.

### Claim 17 (depends on 16)

The machine-readable medium of claim 16, wherein the operations further comprise:
receiving the single packet; and
sending the single packet to another device.

### Claim 18 (depends on 16)

The machine-readable medium of claim 16, wherein the operations further comprise:
receiving the single packet; and
extracting the combined packets based on the identification information.

### Claim 19 (depends on 18)

The machine-readable medium of claim 18, wherein the operations further comprise:
sending each extracted packet to a destination determined by a header of each extracted packet.

### Claim 20 (depends on 14)

The machine-readable medium of claim 14, wherein combining is performed during at least one of a time (i) prior to resynchronization of a Peripheral Component Interconnect (“PCI”) Express link, and (ii) during resynchronization of a PCI Express link.

### Claim 21 (depends on 1)

The method of claim 1, wherein the local computer-bus interconnect protocol is a point-to-point protocol.

### Claim 22 (depends on 1)

The method of claim 1, wherein the single packet is of at least a minimum size required for transmission.