# US 7,609,708 B2 · Dynamic buffer configuration

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- Number: US 7,609,708 B2
- Document ID: US7609708B2
- Status: Granted
- Kind: B2
- Application number: 11/243,366
- Filed: 2005-10-04
- Published: 2007-04-05
- Granted: 2009-10-27
- Earliest claimed: 2005-10-04
- Assignees: Intel Corporation
- Inventors: Choon Yip Soo
- Web page: https://patentgrep.com/patent/US7609708B2

## CPC

- G06F 13/385: {for adaptation of a particular data processing system to different peripheral devices}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Techniques that may be utilized in various computing environments are described. In one embodiment, a buffer is configured dynamically, e.g., during runtime. Other embodiments are also disclosed.

## Claims

### Claim 1

A method comprising:
monitoring, at a performance monitor unit (PMU), write requests to a transmit portion and a receive portion of a buffer;
adjusting, at a buffer manager, a size of the transmit portion and a size of the receive portion of the buffer based on a comparison of a threshold value, corresponding to one of the transmit portion or the receive portion, with a number of buffer full events, corresponding to a different one of the transmit portion or the receive portion, determined at the PMU, wherein the number of buffer full events corresponds to buffer full events of one of the transmit portion or the receive portion; and
determining the threshold value by multiplying a value of the buffer full events by a factor.

### Claim 2 (depends on 1)

The method of claim 1, wherein adjusting the sizes of the transmit and the receive portions comprises generating a buffer configuration signal.

### Claim 3 (depends on 1)

The method of claim 1, wherein adjusting the sizes of the transmit and the receive portions is performed by maintaining a same size of the buffer.

### Claim 4 (depends on 1)

The method of claim 1, further comprising updating one of a transmit full counter corresponding to the transmit portion or a receive full counter corresponding to the receive portion for each occurrence of the buffer full events.

### Claim 5 (depends on 1)

The method of claim 1, further comprising resetting a transmit full counter corresponding to the transmit portion and a receive full counter corresponding to the receive portion if the transmit portion size and the receive portion size are adjusted.

### Claim 6 (depends on 1)

The method of claim 1, wherein adjusting the sizes of the transmit and receive portions of the buffer is performed as long as the size of the transmit and receive portions are above a minimum size.

### Claim 7 (depends on 1)

The method of claim 1, further comprising resetting a transmit full counter corresponding to the transmit portion and a receive full counter corresponding to the receive portion if the transmit portion size and the receive portion size are at a minimum size.

### Claim 8 (depends on 1)

The method of claim 1, wherein adjusting the sizes of the transmit and the receive portions comprises one of:
reducing the size of the transmit portion by a first number of entries and increasing the size of the receive portion by the first number of entries; or
increasing the size of the transmit portion by a second number of entries and increasing the size of the receive portion by the second number of entries.

### Claim 9

An apparatus comprising:
logic circuitry to monitor write requests to a transmit portion and a receive portion of a buffer; and
a buffer manager to adjust a size of the transmit portion and a size of the receive portion of the buffer based on a comparison of a threshold value, corresponding to one of the transmit portion or the receive portion, with a number of buffer full events, corresponding to a different one of the transmit portion or the receive portion, wherein the buffer manager is coupled to receive a signal from the logic circuitry indicating the threshold value is exceeded, wherein the number of buffer full events corresponds to buffer full events of one of the transmit portion or the receive portion and wherein the threshold value is to be determined by multiplying a value of the buffer full events by a factor.

### Claim 10 (depends on 9)

The apparatus of claim 9, further comprising a transmit full counter corresponding to the transmit portion and a receive full counter corresponding to the receive portion.

### Claim 11 (depends on 9)

The apparatus of claim 9, further comprising one or more hardware registers to each store one or more of a transmit full counter corresponding to the transmit portion and a receive full counter corresponding to the receive portion.

### Claim 12 (depends on 9)

The apparatus of claim 9, wherein the transmit and receive portions of the buffer are contiguous.

### Claim 13 (depends on 9)

The apparatus of claim 9, wherein the buffer comprises a first-in, first-out buffer.

### Claim 14 (depends on 9)

The apparatus of claim 9, further comprising one or more processor cores to access data stored in the buffer.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the one or more processor cores are on a same integrated circuit die.

### Claim 16 (depends on 14)

The apparatus of claim 14, wherein the one or more processor cores are processor cores of a symmetrical multiprocessor or an asymmetrical multiprocessor.

### Claim 17

A storage device comprising instructions that when executed on a processor configure the processor to perform operations comprising:
monitoring, at a PMU, write requests to a transmit portion and a receive portion of a buffer;
adjusting, at a buffer manager, a size of the transmit portion and a size of the receive portion of the buffer based on a comparison of a threshold value, corresponding to one of the transmit portion or the receive portion, with a number of buffer full events, corresponding to a different one of the transmit portion or the receive portion, determined at the PMU, wherein the number of buffer full events corresponds to buffer full events of one of the transmit portion or the receive portion; and
determining the threshold value by multiplying a value of the buffer full events by a factor.

### Claim 18 (depends on 17)

The storage device of claim 17, wherein the operations further comprise resetting a transmit full counter corresponding to the transmit portion and a receive full counter corresponding to the receive portion if the transmit portion size and the receive portion size are adjusted.

### Claim 19

A traffic management device comprising:
a switch fabric; and
an apparatus, coupled to the switch fabric, to store data communicated via the switch fabric, the apparatus comprising:
logic to monitor write requests to a transmit portion and a receive portion of a buffer; and
a buffer manager to adjust a size of the transmit portion and a size of the receive portion of the buffer based on a comparison of a threshold value, corresponding to one of the transmit portion or the receive portion, to a number of buffer full events, corresponding to a different one of the transmit portion or the receive portion, wherein the buffer manager is coupled to receive a signal from the logic indicating the threshold value is exceeded, wherein the number of buffer full events corresponds to buffer full events of one of the transmit portion or the receive portion and wherein the threshold value is to be determined by multiplying a value of the buffer full events by a factor.

### Claim 20 (depends on 19)

The traffic management device of claim 19, wherein the switch fabric conforms to one or more of common switch interface (CSIX), advanced switching interconnect (ASI), Hyperlransport, Infiniband, peripheral component interconnect (PCI), Ethernet, Packet-Over-SONET (synchronous optical network), or Universal Test and Operations PHY (physical) Interface for ATM (UTOPIA).

### Claim 21 (depends on 19)

The traffic management device of claim 19, further comprising a transmit full counter corresponding to the transmit portion and a receive full counter corresponding to the receive portion.
