# US 7,609,581 B2 · Semiconductor memory device

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- Number: US 7,609,581 B2
- Document ID: US7609581B2
- Status: Granted
- Kind: B2
- Application number: 11/772,587
- Filed: 2007-07-02
- Published: 2007-12-06
- Granted: 2009-10-27
- Earliest claimed: 2006-03-13
- Assignees: Kabushiki Kaisha Toshiba
- Inventors: Nobuaki Otsuka; Osamu Hirabayashi
- Web page: https://patentgrep.com/patent/US7609581B2

## CPC

- G11C 11/417: for memory cells of the field-effect type
- G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor memory device includes a memory cell array provided in a cell array area and including a plurality of memory cells, a source potential line which applies a source potential to the memory cells, a switching element group provided in the cell array area adjacent to the memory cell array, the switching element group electrically connecting the source potential line to a ground potential line, when the memory cells are in an operation mode, a first P-type MIS transistor connected between the source potential line and the ground potential line, and fixing the source potential when the memory cells are in the sleep mode, and a bias generation circuit provided in a peripheral circuit area, and supplying a first bias potential to the first MIS transistor, the first MIS transistor being provided in the peripheral circuit area.

## Claims

### Claim 1

A semiconductor memory device comprising:
a memory cell array provided in a cell array area and including a plurality of memory cells, each memory cell being of a static type and formed of MIS transistors;
a source potential line which applies a source potential to the memory cells;
a switching element group including a plurality of switching elements and provided in the cell array area adjacent to the memory cell array, the switching element group electrically connecting the source potential line to a power supply potential line, when the memory cells are in an operation mode, and electrically disconnecting the source potential line from a ground potential line, when the memory cells are in a sleep mode;
a first N-type MIS transistor connected between the source potential line and the power supply potential line, and fixing the source potential when the memory cells are in the sleep mode; and
a bias generation circuit provided in a peripheral circuit area outside the cell array area, and supplying a first bias potential to a gate terminal included in the first MIS transistor,
the first MIS transistor being provided in the peripheral circuit area.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1, wherein in the sleep mode, the source potential is fixed to a potential acquired by adding a threshold voltage of the first MIS transistor to the first bias potential.

### Claim 3 (depends on 1)

The semiconductor memory device according to claim 1, wherein the switching elements are formed of second P-type MIS transistors.

### Claim 4 (depends on 1)

The semiconductor memory device according to claim 1, wherein the first bias potential generated by the bias generation circuit reflects a change in a threshold voltage of MIS transistors included in the memory cell.

### Claim 5 (depends on 4)

The semiconductor memory device according to claim 4, wherein:
the memory cell includes an N-type driving MIS transistor and a P-type load MIS transistor; and
the bias generation circuit includes a first replica transistor having a threshold voltage equal to a threshold voltage of the driving MIS transistor or the load MIS transistor.