# US 7,609,580 B2 · Redundancy program circuit and methods thereof

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- Number: US 7,609,580 B2
- Document ID: US7609580B2
- Status: Granted
- Kind: B2
- Application number: 12/314,969
- Filed: 2008-12-19
- Published: 2009-05-07
- Granted: 2009-10-27
- Earliest claimed: 2004-06-30
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Jeong-Sik Nam; Sang-Kyun Park; Kwang-Hyun Kim; Byung-Sik Moon; Won-Chang Jung
- Web page: https://patentgrep.com/patent/US7609580B2

## CPC

- G11C 29/812: {using a reduced amount of fuses}
- G11C 29/787: {using a fuse hierarchy}
- G11C 29/785: {with redundancy programming schemes}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.

## Claims

### Claim 1

A redundancy program circuit, comprising:
a master fuse circuit including a master fuse outputting an operation enable signal to indicate a master fuse operating status;
at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse in response to the operation enable signal; and
a decoding circuit for decoding signal bits of a decoding address in response to the operating status signal and transferring a given logic level along with the decoding address to a decoding output terminal.

### Claim 2 (depends on 1)

The redundancy program circuit of claim 1, wherein the decoding address is decoded from one of an internal address. generated before predecoding and an external address received from an external device.

### Claim 3 (depends on 1)

The redundancy program circuit of claim 1, wherein the decoding circuit includes a plurality of decoders, a number of the plurality of decoders corresponding to a number of signal bits in the decoding address.

### Claim 4 (depends on 3)

The redundancy program circuit of claim 3, wherein each of the plurality of decoders includes at least one NMOS transistor.

### Claim 5 (depends on 4)

The redundancy program circuit of claim 4, wherein the at least one NMOS transistor for each of the plurality of decoders includes channels connected in series.

### Claim 6 (depends on 1)

The redundancy program circuit of claim 1, wherein:
the at least one control fuse circuit includes a plurality of control fuse circuits which are controlled in response to the operation enable signal of the master fuse circuit, the at plurality of control fuse circuits including a number of control fuses corresponding to a number of decoding address signal bits of the decoding address; and
the decoding circuit is one of a plurality of decoding circuits, each of the plurality of decoding circuits outputting the given logic level to a corresponding output terminal.

### Claim 7 (depends on 6)

The redundancy program circuit of claim 6, further comprising:
a combination circuit for gating the logic levels received from the plurality of decoding circuits at the corresponding output terminals and generating a redundancy enable signal as a result of the gating operation.

### Claim 8 (depends on 6)

The redundancy program circuit of claim 6, wherein the number of control fuses within the plurality of control fuse circuits equals the number of decoding address signal bits of the decoding address

### Claim 9 (depends on 7)

The redundancy program circuit of claim 7, wherein the operating status signal includes three control signal pairs when the decoding address includes eight signal bits.

### Claim 10 (depends on 9)

The redundancy program circuit of claim 9, wherein the eight signal bits of the decoding address are decoded by eight combinational logic inputs generated based on the three control signal pairs.

### Claim 11 (depends on 7)

The redundancy program circuit of claim 7, wherein the combination circuit includes an AND gate.

### Claim 12

A method of performing a redundancy program operation, comprising:
generating an operation enable signal;
generating an operating status signal indicating a status of at least one control fuse; and
decoding signal bits of a decoding address in response to the operating status signal and transferring a given logic level associated with a defective memory cell along with the decoding address to a decoding output terminal.