# US 7,609,578 B2 · Quad SRAM based one time programmable memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,609,578 B2 - Document ID: US7609578B2 - Status: Granted - Kind: B2 - Application number: 11/933,073 - Filed: 2007-10-31 - Published: 2009-04-30 - Granted: 2009-10-27 - Earliest claimed: 2007-10-31 - Assignees: Broadcom Corporation - Inventors: Myron Buer; Jonathan Schmitt; Laurentiu Vasiliu - Web page: https://patentgrep.com/patent/US7609578B2 ## CPC - G11C 17/18: Auxiliary circuits, e.g. for writing into memory - G11C 11/419: Read-write [R-W] circuits - G11C 17/146: {Write once memory, i.e. allowing changing of memory content by writing additional bits} - G11C 17/16: using electrically-fusible links - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A quad SRAM based one time programmable memory cell is provided. Prior to programming, the memory cell operates as an SRAM memory cell. After programming, the memory cell operates as a one-time programmable non-volatile memory cell. The memory cell includes a storage element coupled at a first side to a first upper fuse and a first lower fuse and coupled at a second side to a second upper fuse and a second lower fuse. When the first upper fuse and second lower fuse are programmed, the storage element outputs a first value. When the second upper fuse and first lower fuse are programmed, the storage element outputs a second value. After programming the upper fuse acts as a pull-up fuse and the lower fuse acts as a pull-down fuse hold the state of the cell. ## Claims ### Claim 1 A one-time programmable memory cell, comprising: a storage element having a first upper input, a second upper input opposite the first upper input, a first lower input, a second lower input opposite the first lower input, a first output, and a second output opposite the first output; a first fuse coupled to the first upper input, wherein the first fuse, when programmed, acts as a pull-up device on the first output; a second fuse coupled to the second upper input, wherein the second fuse, when programmed, acts as a pull-up device on the second output; a third fuse coupled to the first lower input, wherein the third fuse, when programmed, acts a pull-down device on the first output; and a fourth fuse coupled to the second lower input, wherein the fourth fuse, when programmed, acts a pull-down device on the second output. ### Claim 2 (depends on 1) The one-time programmable memory cell of claim 1, wherein when the first fuse and fourth fuse are programmed, the storage element outputs a first value during a read operation, and when the second fuse and third fuse are programmed, the storage element outputs a second value during a read operation. ### Claim 3 (depends on 1) The one-time programmable memory cell of claim 1 wherein the storage element operates as an SRAM cell when the first fuse, the second fuse, the third fuse, and the fourth fuse are not programmed. ### Claim 4 (depends on 1) The one-time programmable memory cell of claim 1, wherein the first fuse, the second fuse, the third fuse, and the fourth fuse are thin-oxide MOS transistors. ### Claim 5 (depends on 4) The one-time programmable memory cell of claim 4, wherein at least one of the thin-oxide MOS transistors is an NMOS transistor. ### Claim 6 (depends on 4) The one-time programmable memory cell of claim 4, wherein at least one of the thin-oxide MOS transistors is an NMOS transistor with a native VT implant. ### Claim 7 (depends on 4) The one-time programmable memory cell of claim 4, wherein at least one of the thin-oxide MOS transistor is an NMOS transistor in NWELL. ### Claim 8 (depends on 4) The one-time programmable memory cell of claim 4, wherein at least one of the thin-oxide MOS transistors is a PMOS transistor. ### Claim 9 (depends on 1) The one-time programmable memory cell of claim 1, further comprising: a first programming decoder coupled to the third fuse and the second fuse; and a second programming decoder coupled to the fourth fuse and the first fuse. ### Claim 10 (depends on 1) The one-time programmable memory cell of claim 1, wherein the storage element comprises: a first inverter coupled to the first fuse and the third fuse; and a second inverter coupled to the second fuse and the fourth fuse. ### Claim 11 (depends on 1) The one-time programmable memory cell of claim 1 further comprising: a first buffer device coupled between the first fuse and the storage element; a second buffer device coupled between the third fuse and the storage element; a third buffer device coupled between the second fuse and the storage element; and a fourth buffer device coupled between the fourth fuse and the storage element. ### Claim 12 A non-volatile dual SRAM one-time programmable memory device, comprising: a dual SRAM one-time programmable memory block including one or more dual SRAM one-time programmable memory cells, wherein a dual SRAM one-time programmable memory cell operates as an SRAM memory cell prior to programming and operates as a one-time programmable memory cell after programming; an SRAM module coupled to the dual SRAM one-time programmable memory block, wherein the SRAM read/write module is configured to read from and write to one or more dual SRAM one-time programmable memory cells prior to programming; and an one-time programmable module configured to program one or more one-time programmable memory cells and to read one or more one-time programmable memory cells after programming. ### Claim 13 (depends on 12) The memory device of claim 12, wherein a one-time programmable memory cell comprises: a storage element having a first upper input, a second upper input opposite the first upper input, a first lower input, a second lower input opposite the first lower input, a first output, and a second output opposite the first output; a first fuse coupled to the first upper input, wherein the first fuse, when programmed, acts as a pull-up device on the first output; a second fuse coupled to the second upper input, wherein the second fuse, when programmed, acts as a pull-up device on the second output; a third fuse coupled to the first lower input, wherein the third fuse, when programmed, acts a pull-down device on the first output; and a fourth fuse coupled to the second lower input, wherein the fourth fuse, when programmed, acts a pull-down device on the second output. ### Claim 14 (depends on 13) The memory device of claim 13, wherein when the first fuse and fourth fuse are programmed, the storage element outputs a first value during a read operation, and when the second fuse and third fuse are programmed, the storage element outputs a second value during a read operation. ### Claim 15 (depends on 13) The memory device of claim 13, wherein the first fuse, the second fuse, the third fuse, and the fourth fuse are thin-oxide MOS transistors. ### Claim 16 (depends on 15) The memory device of claim 15, wherein at least one of the thin-oxide MOS transistors is an NMOS transistor. ### Claim 17 (depends on 15) The memory device of claim 15, wherein at least one of the thin-oxide MOS transistors is an NMOS transistor with a native VT implant. ### Claim 18 (depends on 15) The memory device of claim 15, wherein at least one of the thin-oxide MOS transistors is an NMOS transistor in NWELL. ### Claim 19 (depends on 15) The memory device of claim 15, wherein at least one of the thin-oxide MOS transistors is a PMOS transistor.