# US 7,609,576 B2 · Semiconductor memory device with refresh trigger > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,609,576 B2 - Document ID: US7609576B2 - Status: Granted - Kind: B2 - Application number: 11/845,337 - Filed: 2007-08-27 - Published: 2008-07-31 - Granted: 2009-10-27 - Earliest claimed: 2007-01-30 - Assignees: Kabushiki Kaisha Toshiba - Inventors: Hiroshi Watanabe; Tatsuya Tanaka - Web page: https://patentgrep.com/patent/US7609576B2 ## CPC - G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 16/3431: {Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor memory device includes a memory cell array including a plurality of memory cell transistors, an X decoder designating a position of an X axis of the memory cell, a Y decoder designating a position of a Y axis crossing the X axis, a controller collectively controlling operations of read, write and erase of the memory cell transistors via the X decoder and the Y decoder, a semiconductor time switch generating an output signal after a predetermined life time elapses without a power source, and a refresh trigger circuit receiving the output signal from the semiconductor time switch, and giving the controller instructions to transfer information stored in one area of the memory cell array to other area thereof to refresh the information. ## Claims ### Claim 1 A semiconductor memory device comprising: a memory cell array including a plurality of memory cell transistors; an X decoder designating a position of an X axis of the memory cell; a Y decoder designating a position of a Y axis crossing the X axis; a controller collectively controlling operations of read, write and erase of the memory cell transistors via the X decoder and the Y decoder; a semiconductor time switch generating an output signal after a predetermined life time elapses without a power source; and a refresh trigger circuit receiving the output signal from the semiconductor time switch, and giving the controller instructions to transfer information stored in one area of the memory cell array to other area thereof to refresh the information. ### Claim 2 (depends on 1) The device according to claim 1, wherein an operation of the device comprises the steps of: initializing the semiconductor time switch by the controller in a power on state to set the lifetime of the semiconductor time switch; leaving the semiconductor time switch in a power off state after said initializing; reading an output signal of the semiconductor time switch in the power on state after said leaving; by checking a difference between the output signal in the power on state and an output signal at said initializing, issue, through the refresh trigger circuit, a refresh signal “0” when the difference is within a predetermined offset, or issue a refresh signal “1” when the difference is out of the predetermined offset. ### Claim 3 (depends on 2) The device according to claim 2, wherein the controller transfers information stored in one area of the memory cell array to other area thereof to refresh the information when the refresh signal is “1” in the power on state. ### Claim 4 (depends on 2) The device according to claim 2, wherein the lifetime of the semiconductor time switch set in said initializing is shorter than a data retention time of the memory cell transistor in association with the semiconductor time switch. ### Claim 5 (depends on 2) The device according to claim 2, wherein the output signal of the semiconductor time switch changes between before and after the lifetime set in said initializing. ### Claim 6 (depends on 1) The device according to claim 1, wherein at said refreshing the information, the semiconductor time switch is re-initialized. ### Claim 7 (depends on 1) The device according to claim 1, wherein the semiconductor time switch and the memory cell transistor are embedded in the same chip, and each has a floating gate. ### Claim 8 (depends on 1) The device according to claim 1, wherein a capacity of the information before said refreshing is equal to a capacity of the information after said refreshing. ### Claim 9 (depends on 1) The device according to claim 1, wherein, when N is set as an arbitrary natural number and a capacity of the information stored is set as N bits, the N bits are assigned to non-continuous addresses on the memory cell array. ### Claim 10 (depends on 1) The device according to claim 1, wherein a block including addresses recording the information is transferred to and rewritten in another block as a whole. ### Claim 11 A semiconductor memory device comprising: a memory cell array including a plurality of memory cell transistors; an X decoder designating a position of an X axis of the memory cell; a Y decoder designating a position of a Y axis crossing the X axis; a controller collectively controlling operations of read, write and erase of the memory cell transistors via the X decoder and the Y decoder; a semiconductor time switch generating an output signal after a predetermined life time elapses without a power source; a refresh trigger circuit receiving the output signal from the semiconductor time switch, and giving the controller instructions to transfer information stored in one area of the memory cell array to other area thereof to refresh the information; and an operational amplifier receiving a refresh signal from the refresh trigger circuit, and making operations of read, write and erase of the memory cell transistors. ### Claim 12 (depends on 11) The device according to claim 11, wherein an operation of the device comprises the steps of: initializing the semiconductor time switch by the operational amplifier in a power on state to set the lifetime of the semiconductor time switch; leaving the semiconductor time switch in a power off state after said initializing; reading an output signal of the semiconductor time switch in the power on state after said leaving; by checking a difference between the output signal in the power on state and an output signal at said initializing, issue, through the refresh trigger circuit, a refresh signal “0” when the difference is within a predetermined offset, or issue a refresh signal “1” when the difference is out of the predetermined offset. ### Claim 13 (depends on 12) The device according to claim 12, wherein the controller transfers information stored in one area of the memory cell array to other area thereof when the refresh signal is “1” in the power on state. ### Claim 14 (depends on 12) The device according to claim 12, wherein the lifetime of the semiconductor time switch set in said initializing is shorter than a data retention time of the memory cell transistor associated with the semiconductor time switch. ### Claim 15 (depends on 12) The device according to claim 12, wherein the output signal of the semiconductor time switch changes between before and after the lifetime set in said initializing. ### Claim 16 (depends on 11) The device according to claim 11, wherein at said refreshing the information, the semiconductor time switch is re-initialized. ### Claim 17 (depends on 11) The device according to claim 11, wherein the semiconductor time switch and the memory cell transistor are embedded in the same chip, and each has a floating gate. ### Claim 18 (depends on 11) The device according to claim 11, wherein a capacity of the information before said refreshing is equal to a capacity of the information after said refreshing. ### Claim 19 (depends on 11) The device according to claim 11, wherein, when N is set as an arbitrary natural number and a capacity of the information stored is set as N bits, the N bits are assigned to non-continuous addresses on the memory cell array. ### Claim 20 (depends on 11) The device according to claim 11, wherein a block including addresses recording the information is transferred to and rewritten in another block as a whole.