# US 7,609,572 B2 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,609,572 B2 - Document ID: US7609572B2 - Status: Granted - Kind: B2 - Application number: 11/963,831 - Filed: 2007-12-22 - Published: 2008-07-31 - Granted: 2009-10-27 - Earliest claimed: 2007-01-31 - Assignees: Hitachi, Ltd.; Elpida Memory, Inc. - Inventors: Hiroaki Nakaya; Riichiro Takemura; Satoru Akiyama; Tomonori Sekiguchi; Masayuki Nakamura; Shinichi Miyatake - Web page: https://patentgrep.com/patent/US7609572B2 ## CPC - G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating - G11C 7/08: Control thereof - G11C 2207/005: Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced. ## Claims ### Claim 1 A semiconductor memory device comprising: a sense amplifier; a plurality of memory cell arrays; a shared MOS transistor selecting one of the memory cell arrays arranged on both sides of the sense amplifier; and a control circuit controlling operation of the shared MOS transistor, wherein the control circuit performs control of setting a gate voltage of the shared MOS transistor from first potential to second potential of a word line boosting power source at sense operation by the sense amplifier, setting the gate voltage of the shared MOS transistor from the second potential to third potential after predetermined time elapsed and returning the gate voltage of the shared MOS transistor from the third potential to the first potential when re-coupling the memory cell arrays and the sense amplifier. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein the second potential is set between the first potential and ground potential. ### Claim 3 (depends on 1) The semiconductor memory device according to claim 1, wherein the second potential is set between the first potential and power source voltage. ### Claim 4 (depends on 1) The semiconductor memory device according to claim 1, wherein the third potential is set between the second potential and ground potential. ### Claim 5 (depends on 1) The semiconductor memory device according to claim 1, wherein the third potential is set between the first potential and ground potential. ### Claim 6 (depends on 1) The semiconductor memory device according to claim 1, wherein the third potential is set between the first potential and power source voltage. ### Claim 7 (depends on 1) The semiconductor memory device according to claim 1, wherein data is read by a column selection signal while the gate voltage of the shared MOS transistor is controlled. ### Claim 8 (depends on 1) The semiconductor memory device according to claim 1, wherein the control circuit controls the gate voltage of the shared MOS transistor using a column selection signal. ### Claim 9 (depends on 1) The semiconductor memory device according to claim 1, wherein a bit line overdrive system is adopted. ### Claim 10 (depends on 9) The semiconductor memory device according to claim 9, wherein data is read by a column selection signal while overdriving a bit line. ### Claim 11 (depends on 9) The semiconductor memory device according to claim 9, wherein a bit line overdrive is terminated before termination of the control of the gate voltage of the shared MOS transistor. ### Claim 12 (depends on 9) The semiconductor memory device according to claim 9, wherein a bit line overdrive is terminated after termination of the control of the gate voltage of the shared MOS transistor. ### Claim 13 A semiconductor memory device comprising: a sense amplifier; a plurality of memory cell arrays; shared MOS transistors selecting one of the memory cell arrays arranged on both sides of the sense amplifier; and a control circuit controlling operation of the shared MOS transistors, wherein the control circuit performs control of setting gate voltages of the shared MOS transistors to second potential between first potential of a word line boosting power source and ground potential in a standby state, setting the gate voltages of the shared MOS transistors in a non-selected memory cell array side to the ground potential after command input, setting the gate voltages of the shared MOS transistors in a selected memory cell array side from the second potential to the first potential when re-coupling the memory cell arrays and the sense amplifier and returning gate voltages of a selected side shared MOS transistor and a non-selected side shared MOS transistor to the second potential again in a standby. ### Claim 14 (depends on 13) The semiconductor memory device according to claim 13, wherein the second potential is set between power source voltage and the ground potential. ### Claim 15 (depends on 13) The semiconductor memory device according to claim 13, wherein the control circuit controls respective gate voltages of the shared MOS transistors on both sides of the sense amplifier at different timings. ### Claim 16 (depends on 13) The semiconductor memory device according to claim 13, wherein the control circuit controls the gate voltages of the shared MOS transistors using a column selection signal. ### Claim 17 (depends on 13) The semiconductor memory device according to claim 13, wherein a bit line overdrive system is adopted. ### Claim 18 (depends on 17) The semiconductor memory device according to claim 17, wherein data is read by a column selection signal while overdriving a bit line. ### Claim 19 (depends on 17) The semiconductor memory device according to claim 17, wherein a bit line overdrive is terminated before termination of the control of the gate voltages of the shared MOS transistors. ### Claim 20 (depends on 17) The semiconductor memory device according to claim 17, wherein a bit line overdrive is terminated after termination of the control of the gate voltages of the shared MOS transistors.