# US 7,609,568 B2 · Method and device for securing an integrated circuit, in particular a microprocessor card

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,609,568 B2
- Document ID: US7609568B2
- Status: Granted
- Kind: B2
- Application number: 11/493,865
- Filed: 2006-07-25
- Published: 2007-02-08
- Granted: 2009-10-27
- Earliest claimed: 2005-07-26
- Assignees: STMicroelectronics S.r.l.
- Inventors: Mathieu Lisart; Nicolas Demange
- Web page: https://patentgrep.com/patent/US7609568B2

## CPC

- G06F 21/556: {involving covert channels, i.e. data leakage between processes (inhibiting the analysis of circuitry or operation with measures against power attack G06F21/755)}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 7/24: Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
- G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method processes parallel electrical signals, using parallel processing circuits that process successive cycles of electrical signals according to a rule for allocating electrical signals to the processing circuits. The method comprises, between the processing cycles, a step of modifying the rule for allocating electrical signals to the processing circuits, so that a processing circuit processes electrical signals of different ranks during different processing cycles. The method can be applied particularly to secure a memory during read phases of the memory and of an integrated circuit with a microprocessor using such a memory.

## Claims

### Claim 1

A reading method, comprising:
selecting memory cells within a memory,
applying electrical signals, each being representative of a state of one of the selected memory cells, to memory cell read circuits arranged to read the selected memory cells in parallel and supply a binary output signal each, representative of the state of the memory cell to which it is linked, each electrical signal having a determined rank, and
modifying a rule for allocating the electrical signals to the read circuits, so that each read circuit processes electrical signals of different ranks during different reading cycles.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the allocation rule is randomly or pseudo-randomly modified every T reading cycles in order not to be predictable, T being a constant or variable integer superior or equal to 1.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the number of read circuits is equal to the number of electrical signals to be processed, each read circuit being allocated to the processing of one electrical signal only at each reading cycle, without read circuits redundancy.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the step of modifying the allocation rule comprises a step of applying a first permutation to at least one part of the electrical signals to be processed.

### Claim 5 (depends on 4)

The method according to claim 4, wherein:
the read circuits supply output signals, each of a determined rank; and
the step of modifying the allocation rule comprises a step of applying a second permutation to the output signals, to organize the output signals in a predetermined invariant order.

### Claim 6 (depends on 4)

The method according to claim 4, wherein the first permutation is performed by multiplexers.

### Claim 7 (depends on 1)

The method according to claim 1, comprising steps of:
defining groups of electrical signals and groups of read circuits, each group of read circuits being allocated to the processing of a group of signals;
defining, within each group of electrical signals, a rule for allocating each electrical signal of the group to one read circuit of the group of read circuits allocated to the group of signals; and
modifying the rule for allocating electrical signals within at least one group of signals between two different reading cycles.

### Claim 8 (depends on 7)

The method according to claim 7, wherein the number of read circuits in each group of read circuits is equal to the number of electrical signals in each group of electrical signals, each group of read circuits being allocated to the processing of a group of electrical signals without redundancy of read circuits.

### Claim 9 (depends on 1)

The method according to claim 1, comprising:
providing permutable electrical paths between the memory cells and the read circuits,
applying a first permutation to at least one part of the electrical paths, to modify the order in which the selected memory cells are linked to the read circuits, and
applying a second permutation to the output signals supplied by the read circuits, so that the output signals are supplied in a predetermined invariant order.

### Claim 10

A method for reading data from a memory comprising:
selecting a plurality of memory cells to be read, each memory cell supplying an electrical signal representative of a data value of the cell;
routing the electrical signal to respective read circuits according to a routing rule; and
modifying the routing rule between read cycles.

### Claim 11 (depends on 10)

The method according to claim 10 wherein the routing rule is modified every T read cycles.

### Claim 12 (depends on 10)

The method according to claim 10 wherein T is a constant.

### Claim 13 (depends on 10)

The method according to claim 10 wherein T is a variable.

### Claim 14 (depends on 10)

The method according to claim 10 comprising:
routing the electrical signals to the read circuits via a first multiplexer; and
modifying the routing rule via a selection signal sent to the first multiplexer.

### Claim 15 (depends on 14)

The method according to claim 14 wherein each read circuit supplies an output signal to a second multiplexer, the second multiplexer being configured to output the signals in a predetermined order based on the selection signal.

### Claim 16

A method comprising:
reading in parallel, using a plurality of read circuits, selected memory cells according to a rule for allocating electrical signals to the read circuits;
supplying binary output signals from the read circuits, respectively, based on the reading; and
applying a permutation to at least one part of the electrical signals to the read circuits and modifying the rule for allocating electrical signals to the read circuits, the rule being modified between successive reading cycles.

### Claim 17 (depends on 16)

The method according to claim 16, wherein the number of read circuits is equal to the number of electrical signals to be processed, each read circuit processing one electrical signal only at each reading cycle, without redundancy of read circuits.

### Claim 18 (depends on 16)

The method according to claim 16, wherein the applying includes modifying the rule randomly or pseudo-randomly every T reading cycles.

### Claim 19 (depends on 18)

The method according to claim 18, wherein T is a variable integer, superior or equal to 1.

### Claim 20 (depends on 16)

The method according to claim 16, wherein the permutation is a first permutation, the method further comprising:
organizing the output signals in an invariant order by applying a second permutation to the output signals.

### Claim 21 (depends on 16)

The method according to claim 16, further comprising:
defining groups of the electrical signals and groups of the read circuits, each group of read circuits being allocated to the processing of a corresponding group of the groups of electrical signals;
defining, within each group of electrical signals, a rule for allocating each electrical signal of the group to one read circuit of the group of read circuits allocated to the group of electrical signals; and
modifying the rule for allocating electrical signals within at least one group of signals between two different reading cycles.

### Claim 22 (depends on 21)

The method according to claim 21, wherein the number of read circuits in each group of read circuits is equal to the number of electrical signals in each group of electrical signals, each group of read circuits being allocated to the processing of a group of electrical signals without redundancy of read circuits.

### Claim 23 (depends on 2)

The method according to claim 2 wherein T is a variable.