# US 7,609,566 B2 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,609,566 B2 - Document ID: US7609566B2 - Status: Granted - Kind: B2 - Application number: 11/819,804 - Filed: 2007-06-29 - Published: 2008-07-03 - Granted: 2009-10-27 - Earliest claimed: 2007-01-03 - Assignees: Hynix Semiconductor Inc. - Inventors: Jae-Hyuk Im - Web page: https://patentgrep.com/patent/US7609566B2 ## CPC - G11C 5/145: {Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence)} - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 29/021: {in voltage or current generators} - G11C 29/028: {with adaption or trimming of parameters} - G11C 11/401: forming cells needing refreshing or charge regeneration, i.e. dynamic cells - G11C 2211/4067: Refresh in standby or low power modes - G11C 2211/4068: Voltage or leakage in refresh operations - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor memory device includes a charge pumping circuit, a level sensor, an oscillator, and a pumping control signal generator. The charge pumping circuit performs a negative-pumping operation to an external power in order to generate an internal voltage having a level lower than the external power. The level sensor senses a level of the internal voltage corresponding to a level of an adjusted reference voltage during a refresh mode. The oscillator generates a period signal in response to a sensing signal of the level sensor. The pumping control signal generator controls the operation of the charge pumping circuit in response to the period signal. ## Claims ### Claim 1 A semiconductor memory device, comprising: a charge pumping circuit for negative-pumping an external power to generate an internal voltage with a level lower than the external power; a level sensor for receiving a self refresh signal and sensing a level of the internal voltage corresponding to a level of an adjusted reference voltage during a refresh mode; an oscillator for generating a period signal in response to a sensing signal of the level sensor; and a pumping control signal generator for controlling the operation of the charge pumping circuit in response to the period signal. ### Claim 2 (depends on 1) The semiconductor memory device as recited in claim 1, wherein the level sensor includes: a feedback circuit for providing a level of the internal voltage on the basis of the level of the adjusted reference voltage as a feedback voltage; a level controller for providing control signals for controlling a level of the feedback voltage during the refresh mode; and a differential amplifier for taking the feedback voltage and its inverted feedback voltage as differential inputs to output the sensing signal. ### Claim 3 (depends on 2) The semiconductor memory device as recited in claim 2, wherein the level controller includes: a first NAND gate taking a self refresh interval signal as the self refresh signal and a first level adjustment signal; a first inverter for inverting an output signal of the first NAND gate to output a down-control signal; a second NAND gate taking the self refresh interval signal and a second level adjustment signal; and a second inverter for inverting an output signal of the second NAND gate to provide an up-control signal. ### Claim 4 (depends on 3) The semiconductor memory device as recited in claim 3, wherein the first and the second level adjustment signals are selected so that a leakage current is minimized in a test step of wafer level, and set by a fuse option or a metal option. ### Claim 5 (depends on 4) The semiconductor memoiy device as recited in claim 4, wherein the feedback circuit includes: first to fourth PMOS transistors whose each gate takes a ground voltage and which are connected in series between a reference voltage and an output node; fifth to eighth PMOS transistors whose each gate takes the internal voltage and which are connected in series between the output node and the ground voltage; a first NMOS transistor whose gate receives the down-control signal and which is connected in parallel with the first PMOS transistor; and a second NMOS transistor whose gate accepts the up-control signal and which is connected in parallel with the eighth PMOS transistor. ### Claim 6 (depends on 5) The semiconductor memory device as recited in claim 5, further comprising a reference voltage generator for generating the reference voltage having a stable level regardless of the external power. ### Claim 7 A driving method of a semiconductor memory device, comprising: performing negative-pumping operation to an external power in order to generate a bulk voltage of memory cell; sensing a level of the bulk voltage in response to an adjusted reference voltage; and controlling the negative-pumping operation so that the bulk voltage has a level corresponding to the adjusted reference voltage, wherein the adjusted reference voltage has a different voltage level for a self refresh mode than a level of the reference voltage for a normal mode. ### Claim 8 (depends on 7) The driving method as recited in claim 7, wherein sensing the level of the bulk voltage includes: dividing a voltage difference between the bulk voltage and the adjusted reference voltage to produce a feedback voltage; adjusting a level of the feedback voltage during the self refresh mode; and generating a sensing signal depending on the level of the feedback voltage. ### Claim 9 (depends on 8) The driving method as recited in claim 8, wherein controlling the negative-pumping operation is perfonned by repeating the negative-pumping operation while the sensing signal is enabled.