# US 7,609,563 B2 · Simultaneous read circuit for multiple memory cells > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,609,563 B2 - Document ID: US7609563B2 - Status: Granted - Kind: B2 - Application number: 12/073,056 - Filed: 2008-02-28 - Published: 2008-09-04 - Granted: 2009-10-27 - Earliest claimed: 2004-01-29 - Assignees: Micron Technology, Inc. - Inventors: Kristy A. Campbell; Terry L. Gilton - Web page: https://patentgrep.com/patent/US7609563B2 ## CPC - G11C 11/16: using elements in which the storage effect is based on magnetic spin effect - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - G11C 11/5664: {using organic memory material storage elements} - G11C 11/5678: {using amorphous/crystalline phase transition storage elements} - G11C 11/5685: {using storage elements comprising metal oxide memory material, e.g. perovskites} - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites} - G11C 13/0009: {RRAM elements whose operation depends upon chemical change} - G11C 13/0014: {comprising cells based on organic memory material} - G11C 13/0016: {comprising polymers} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} - G11C 2207/066: Frequency reading type sense amplifier - G11C 2213/31: Material having complex metal oxide, e.g. perovskite structure - G11C 2213/77: Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used - G11C: STATIC STORES (semiconductor memory devices H10B) - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ## Abstract A memory device including a simultaneous read circuit design for multiple memory cells on a single interconnect using a fast fourier transform analysis circuit. The simultaneous read circuit can be used with any memory type storing information as an energy-absorbing state. ## Claims ### Claim 1 A memory circuit, comprising: a plurality of multi-bit memory cells; a conductor line electrically connected to each of the plurality of multi-bit memory cells; and a fast fourier transform analysis circuit electrically connected to the conductor line configured to interpret data corresponding to at least one of the bits stored in each of the plurality of memory cells in response to a read signal applied to the conductor line. ### Claim 2 (depends on 1) The memory circuit of claim 1, wherein the multi-bit memory cells comprise a host material incorporating at least two species of metal ions, the host material and the metal ions being configured to detectably absorb an amount of energy corresponding to a separation in energy of electron spin levels of the metal ions at zero field. ### Claim 3 (depends on 1) The memory circuit of claim 1, wherein each of the bits stored in each of the plurality of memory cells is independently accessible by tailoring a rise time of the read signal. ### Claim 4 (depends on 3) The memory circuit of claim 3, wherein the species of metal ions comprise Cu+2 and one of Mn+2 and Mn+3. ### Claim 5 (depends on 3) The memory circuit of claim 3, wherein the host material is germanium selenide. ### Claim 6 (depends on 1) The memory circuit of claim 1, wherein a number of bits storable in each of the multi-bit memory cells is equal to the number of species of metal ions incorporated into the host material. ### Claim 7 A memory circuit, comprising: a plurality of multi-bit memory cells, each comprising a first electrode and a second electrode electrically coupled to a host material incorporating at least two species of metal ions, the metal ions exhibiting zero field splitting resonance in response to an activation pulse, the host material and the metal ions being configured to store multiple bits of data as a plurality of energy-absorbing states and non-energy-absorbing states; a conductor line electrically connected to each of the plurality of memory cells; and a fast fourier transform analysis circuit electrically connected to the conductor line and configured to interpret data corresponding to one of the bits stored in each of the plurality of memory cells in response to a read signal applied to the conductor line. ### Claim 8 (depends on 7) The memory circuit of claim 7, wherein a number of bits storable in each of the multi-bit memory cells is equal to the number of species of metal ions incorporated into the host material. ### Claim 9 (depends on 7) The memory circuit of claim 7, wherein the species of metal ions comprise Cu+2 and one of Mn+2 and Mn+3. ### Claim 10 (depends on 7) The memory circuit of claim 7, wherein the host material is Ge40Se60 incorporating about 3 wt. % Mn+2 and 3 wt. % Cu+2 as the species of metal ions. ### Claim 11 (depends on 7) The memory circuit of claim 7, wherein the host material is Ge40Se60 incorporating about 3 wt. % Mn+3 and 3 wt. % Cu+2 as the species of metal ions. ### Claim 12 (depends on 7) The memory circuit of claim 7, wherein the host material and the metal ions are configured to absorb a detectable amount of energy corresponding to a separation in energy of the electron spin levels of the metal ions at zero field. ### Claim 13 (depends on 7) The memory circuit of claim 7, wherein each of the plurality of multi-bit memory cells is configured to be programmed to energy-absorbing states by a light pulse. ### Claim 14 (depends on 7) The memory circuit of claim 7, wherein each of the plurality of multi-bit memory cells is configured to be programmed to energy-absorbing states by an electrical pulse. ### Claim 15 (depends on 7) The read memory circuit of claim 7, wherein the fast fourier transform analysis circuit provides a signature pulse out potential shape during a read operation, the signature pulse out potential shape representing the programmed state of at least one of the bits of each of the plurality of multi-bit memory cells corresponding to an activation pulse strength and a rise time of the read signal. ### Claim 16 (depends on 15) The read memory circuit of claim 15, wherein the signature pulse out potential shape is defined by the programmed state of at least one of the bits of each of the plurality of multi-bit memory cells and the location of each multi-bit memory cell along the conductor line. ### Claim 17 A method of simultaneously reading a plurality of multi-bit memory cells, comprising: providing a plurality of multi-bit memory cells, each being programmable to a plurality of energy-absorbing states and non-energy-absorbing states; programming at least one of the plurality of multi-bit memory cells to at least one of the plurality of energy-absorbing states; and simultaneously reading one of the bits stored in each of the plurality of multi-bit memory cells by sensing the absorption or transmission of a read energy pulse through each of the plurality of memory cells. ### Claim 18 (depends on 17) The method of claim 17, wherein each of the multi-bit memory cells comprises a host material incorporating at least two species of metal ions, the metal ions exhibiting zero field splitting resonance in response to an activation pulse, the host material and the metal ions being configured to store multiple bits of data as a plurality of energy-absorbing states and non-energy-absorbing states. ### Claim 19 (depends on 18) The method of claim 18, wherein a number of bits readable in each of the multi-bit memory cells is equal to the number of species of metal ions incorporated into the host material. ### Claim 20 (depends on 17) The method of claim 17, further comprising using a fast fourier transform circuit to interpret the read energy pulse through the plurality of multi-bit memory cells as an output signature defined by the programmed state and location on a conductor line of each multi-bit memory cell.