# US 7,609,560 B2 · Sensing of memory cells in a solid state memory device by fixed discharge of a bit line > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,609,560 B2 - Document ID: US7609560B2 - Status: Granted - Kind: B2 - Application number: 11/943,136 - Filed: 2007-11-20 - Published: 2009-05-21 - Granted: 2009-10-27 - Earliest claimed: 2007-11-20 - Assignees: Micron Technology, Inc. - Inventors: Frankie F. Roohparvar - Web page: https://patentgrep.com/patent/US7609560B2 ## CPC - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract In one or more of the disclosed embodiments, a memory device is provided that reads a target memory cell by first charging the series string of memory cells to which the target memory cell is coupled. A fixed unit of charge is removed from the charged bit line. The bit line is sensed by sense amplifiers to determine the read voltage (i.e., threshold voltage) applied to a word line coupled to the target cell in order to turn on the target cell. The threshold voltage is indicative of the analog voltage stored on the target memory cell. ## Claims ### Claim 1 A method for sensing of a target memory cell, the method comprising: charging a series string of memory cells coupled to the target memory cell by clocking a select gate drain transistor with a clocking signal coupled to a control gate of the transistor such that the transistor turns on and off in response to the clocking signal; discharging the series string by a fixed unit of charge after the series string is charged; and sensing a current on the bit line in response to the target memory cell turning on. ### Claim 2 (depends on 1) The method of claim 1 wherein discharging the series string comprises clocking a select gate source transistor with a positive-going pulse coupled to a control gate of the transistor such that the transistor turns on with a rising edge of the clocking signal and the transistor turns off with a falling edge of the clocking signal. ### Claim 3 (depends on 1) The method of claim 1 wherein a length of the positive-going pulse coupled to the control gate of the select gate drain transistor and the positive-going pulse coupled to control gate of the select gate source transistor transfers charge to ground. ### Claim 4 (depends on 1) The method of claim 1 wherein a rising edge of the select gate source clocking one of either coincides with a falling edge of the select gate drain clocking or is delayed from the falling edge of the select gate drain clocking. ### Claim 5 (depends on 1) The method of claim 1 and further including determining a bias voltage on a word line of the target memory cell that causes the target memory cell to turn on. ### Claim 6 (depends on 5) The method of claim 5 wherein the bias voltage is a threshold voltage of the target memory cell. ### Claim 7 (depends on 1) The method of claim 1 wherein clocking of the select gate drain and select gate source transistors is initiated during a read operation of the target memory cell. ### Claim 8 A method for operating a memory device, the method comprising: programming, to a first voltage level, a target memory cell of a series string of memory cells coupled to a bit line; verifying that the target memory cell is programmed to the first voltage level; and sensing the target memory cell by: precharging the bit line to a second voltage level; charging the series string to the bit line; discharging the series string by a fixed quantity of charge/discharge cycles; and sensing a current on the bit line in response to a read voltage applied to a word line coupled to the target memory cell. ### Claim 9 (depends on 8) The method of claim 8 wherein the memory device is a NAND flash memory device. ### Claim 10 (depends on 8) The method of claim 8 wherein the second voltage level is a supply voltage for the memory device. ### Claim 11 (depends on 8) The method of claim 8 wherein the first voltage level is representative of a digital bit pattern to be stored in the target memory cell. ### Claim 12 (depends on 8) The method of claim 8 wherein charging the series string to the bit line comprises enabling a select gate drain transistor for a first time such that a charge can be transferred from the bit line to the series string of memory cells. ### Claim 13 (depends on 12) The method of claim 12 wherein discharging the series string comprises enabling a select gate source transistor for a second time such that the fixed unit of charge is removed from the series string of memory cells to a source line. ### Claim 14 A solid state memory device comprising: an array of memory cells organized in rows of memory cells coupled to word lines and series strings of memory cells coupled to bit lines; control circuitry for the array of memory cells wherein the control circuitry is adapted to sense a current on a bit line coupled to a target memory cell, in order to determine a representative analog voltage programmed into the target memory cell, by transferring a charge from the bit line to a series string of memory cells comprising the target memory cell then removing a fixed unit of charge from the bit line; and a read/write channel coupled between the control circuitry and the array of non-volatile memory cells, the read/write channel having digital-to-analog conversion circuitry and analog-to-digital conversion circuitry. ### Claim 15 (depends on 14) The solid state memory device of claim 14 wherein the array of non-volatile memory cells is organized in a NAND architecture. ### Claim 16 (depends on 14) The solid state memory device of claim 14 wherein the control circuitry is further adapted to receive a digital bit pattern to be programmed into a target memory cell, submit the digital bit pattern to the read/write channel for conversion to the representative analog voltage, and program the representative analog voltage into the target memory cell. ### Claim 17 (depends on 14) The solid state memory device of claim 14 wherein the control circuitry controls enablement of a select gate drain transistor to transfer charge from the bit line and controls enablement of a select gate source transistor to remove the fixed unit of charge. ### Claim 18 (depends on 17) The solid state memory device of claim 17 wherein each series string of memory cells comprises a memory cell, between the target memory cell and the select gate source transistor, that is unused.