# US 7,609,556 B2 · Non-volatile memory with improved program-verify operations

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- Number: US 7,609,556 B2
- Document ID: US7609556B2
- Status: Granted
- Kind: B2
- Application number: 11/955,624
- Filed: 2007-12-13
- Published: 2008-04-24
- Granted: 2009-10-27
- Earliest claimed: 2005-12-29
- Assignees: SanDisk Corporation
- Inventors: Siu Lung Chan
- Web page: https://patentgrep.com/patent/US7609556B2

## CPC

- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/3454: {Arrangements for verifying correct programming or for detecting overprogrammed cells}
- G11C 2211/5621: Multilevel programming verification
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify operation relative to a demarcation threshold level for demarcating between two memory states, the verify operation includes a sequence of two verify sub-cycles, the first sub-cycle performing a verify relative to a first threshold level at a predetermined margin below the demarcation threshold level and the second sub-cycle performing a verify relative to a second threshold level which is identical to the demarcation threshold level. Unlike conventional cases, the second sub-cycle is not performed until any one memory cell of the group has been verified to pass the first threshold.

## Claims

### Claim 1

A non-volatile memory, comprising:
an array of memory cells to be programmed relative to a demarcation threshold voltage;
a programming circuit for applying a programming pulse to the group of memory cells;
a sensing circuit with a first configuration to verify the cells of the group relative to a first reference threshold voltage at a predetermined margin below that of the demarcation threshold voltage;
a memory controller alternately controlling applying a programming pulse and verifying the programmed result for the group of memory cells in parallel;
said verifying further comprises:
a first verifying relative to a first reference threshold voltage at a predetermined margin below that of the demarcation threshold voltage;
reducing the rate of subsequent programming of the cell that has been verified relative to the first reference threshold voltage;
a second verifying relative to the demarcation threshold voltage; and
inhibiting the memory cell that has been verified relative to the demarcation threshold voltage from further programming; and wherein:
said second verifying is skipped until at least one of the memory cells of the group has been verified relative to the first threshold voltage.

### Claim 2 (depends on 1)

The non-volatile memory as in claim 1, further comprising:
a set of associated bit lines for accessing the group of memory cells; and
a voltage supply for raising a voltage on the bit line of the cell that has been verified relative to the first reference threshold voltage in order to slow subsequent programming of the cell.

### Claim 3 (depends on 1)

The non-volatile memory as in claim 1, further comprising:
a set of associated bit lines for accessing the group of memory cells; and wherein
said program inhibit circuit includes raising the bit line associated with the memory cell to be inhibited substantially to the a supply voltage while the cells not inhibited have their bit lines at substantially zero voltage.

### Claim 4 (depends on 1)

The non-volatile memory as in claim 1, wherein said programming pulse is monotonically increasing with every pulse.

### Claim 5 (depends on 1)

The non-volatile memory as in claim 1, wherein said group of memory cells is a portion of a flash EEPROM.

### Claim 6 (depends on 1)

The non-volatile memory as in claim 1, wherein said group of memory cells is embodied in a memory card.

### Claim 7 (depends on 1)

The non-volatile memory as in claim 1, wherein said group of memory cells is from a memory array organized with a NAND structure.

### Claim 8 (depends on 1)

The non-volatile memory as in claim 1, wherein individual memory cells each stores more than one bit of data.