# US 7,609,553 B2 · NAND flash memory device with burst read latency function > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,609,553 B2 - Document ID: US7609553B2 - Status: Granted - Kind: B2 - Application number: 11/511,275 - Filed: 2006-08-29 - Published: 2007-03-15 - Granted: 2009-10-27 - Earliest claimed: 2005-09-12 - Assignees: Samsung Electronics Co., Ltd. - Inventors: Sang-won Hwang - Web page: https://patentgrep.com/patent/US7609553B2 ## CPC - G11C 16/32: Timing circuits - G11C 7/1027: {Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses} - G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits} - G11C 7/1066: {Output synchronization} - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A NAND flash memory device may include an interface block which receives an external read enable signal to output an internal clock signal during a read operation. The NAND flash memory device may also include a buffer clock controlling circuit which operates in response to a data output enable signal and the internal clock signal. The NAND flash memory device may also include a buffer clock generating circuit which receives the internal clock signal and which generates first and second buffer clock signals according to a control output of the buffer clock control circuit. The NAND flash memory device may also include a data output buffer circuit which sequentially outputs read data in response to one of the first and second buffer clock signals, wherein the buffer clock controlling circuit controls the buffer clock generating circuit to generate the second buffer clock signal having a single pulse when the data output enable signal is activated. ## Claims ### Claim 1 A NAND flash memory device comprising: an interface block which receives an external read enable signal to output an internal clock signal during a read operation; a buffer clock controlling circuit which operates in response to a data output enable signal and the internal clock signal; a buffer clock generating circuit which receives the internal clock signal and which generates first and second buffer clock signals according to a control output of the buffer clock control circuit; and a data output buffer circuit which sequentially outputs read data in response to one of the first and second buffer clock signals, wherein the buffer clock controlling circuit controls the buffer clock generating circuit to generate the second buffer clock signal having a single pulse when the data output enable signal is activated. ### Claim 2 (depends on 1) The NAND flash memory device of claim 1, wherein the data output buffer circuit is synchronized with the second buffer clock signal to output data to a data pad. ### Claim 3 (depends on 1) The NAND flash memory device of claim 1, wherein when the first buffer clock signal having zero phase difference with respect to the internal clock signal is generated, the buffer clock controlling circuit controls the buffer clock generating circuit to transfer the internal clock signal to the data output buffer circuit. ### Claim 4 (depends on 1) The NAND flash memory device of claim 1, wherein when the first buffer clock signal having zero phase difference with respect to the internal clock signal is not generated, the buffer clock controlling circuit controls the buffer clock generating circuit so that the internal clock signal as the second buffer clock signal is transferred to the data output buffer circuit. ### Claim 5 (depends on 1) The NAND flash memory device of claim 1, wherein the buffer clock generating circuit activates a clock enable signal in response to a first high-to-low transition of the internal clock signal. ### Claim 6 (depends on 5) The NAND flash memory device of claim 5, wherein the buffer clock generating circuit comprises: a first clock generator which generates the first buffer clock signal in response to the clock enable signal and generates a lock flag signal indicating whether a first buffer clock signal having zero phase difference with respect to the internal clock signal is generated; a second clock generator which generates the second buffer clock signal in response to the data output enable signal, the internal clock signal, and a lock flag signal; and a selector which transfers one of the first buffer clock signal and the second buffer clock signal according to a control output of the buffer clock controlling circuit. ### Claim 7 (depends on 6) The NAND flash memory device of claim 6, wherein the buffer clock controlling circuit controls the selector to transfer the second buffer clock signal with a single pulse to the data output buffer circuit before the lock flag signal is generated. ### Claim 8 (depends on 6) The NAND flash memory device of claim 6, wherein the buffer clock controlling circuit controls the selector to transfer the first buffer clock signal to the data output buffer circuit when the lock flag signal is generated. ### Claim 9 (depends on 6) The NAND flash memory device of claim 6, wherein the buffer clock controlling circuit controls the data output buffer circuit to transfer the internal clock signal as the second buffer clock signal to the data output buffer circuit after the lock flag signal is not generated and a burst read latency time passed. ### Claim 10 (depends on 6) The NAND flash memory device of claim 6, wherein when the lock flag signal is not generated, the buffer clock controlling circuit deactivates the clock enable signal to deactivate the first buffer clock generator. ### Claim 11 (depends on 6) The NAND flash memory device of claim 6, wherein the burst read latency time is varied by changing an activation time of the clock enable signal. ### Claim 12 (depends on 6) The NAND flash memory device of claim 6, wherein the first clock generating circuit includes a delay synchronization loop circuit. ### Claim 13 (depends on 6) The NAND flash memory device of claim 6, wherein the buffer clock controlling circuit generates a count-up controlling signal in response to the first high-to-low transition of the internal clock signal after the clock enable signal is activated. ### Claim 14 (depends on 13) The NAND flash memory device of claim 13, further comprising an address counter which receives an external address during a read operation to sequentially generate one or more internal addresses, wherein the address counter is synchronized with the internal clock signal to sequentially generate the one or more internal addresses when the count-up controlling signal is activated. ### Claim 15 (depends on 14) The NAND flash memory device of claim 14, further comprising: a page buffer circuit which reads page data from a memory cell array; and a column selection circuit which selects the page data of the page buffer circuit by a predetermined unit in response to an internal address outputted from the address counter and outputs the selected data as read data to the data output buffer circuit. ### Claim 16 A memory system comprising a NAND flash memory device, and a memory controller which outputs a read enable signal to the NAND flash memory device during a read operation and which takes data from the NAND flash memory device after a burst latency time passed, wherein the NAND flash memory device comprises: an interface block which receives the read enable signal to output an internal clock signal; a buffer clock controlling circuit which operates in response a data output enable signal and the internal clock signal; a buffer clock generating circuit which receives the internal clock signal and which generates first and second buffer clock signals according to a control output of the buffer clock controlling circuit; and a data output buffer circuit which sequentially outputs read data in response to one of the first and second buffer clock signals. ### Claim 17 (depends on 16) The memory system of claim 16, wherein the buffer clock controlling circuit controls the buffer clock generating circuit to generate the second buffer clock signal with a single pulse when the data output enable signal is activated, and wherein the buffer clock controlling circuit controls the buffer clock generating circuit to generate the first buffer clock signal having zero phase difference with respect to the internal clock signal after the read enable signal is inputted and a burst read latency time has passed. ### Claim 18 (depends on 17) The memory system of claim 17, wherein the data output buffer circuit is synchronized with the second buffer clock signal to output data to a data pad. ### Claim 19 (depends on 17) The memory system of claim 17, wherein when the first buffer clock signal having zero phase difference with respect to the internal clock signal is generated, the buffer clock controlling circuit controls the buffer clock generating circuit to transfer the first buffer clock signal to the data output buffer circuit. ### Claim 20 (depends on 17) The memory system of claim 17, wherein when the first buffer clock signal having zero phase difference with respect to the internal clock signal is not generated, the buffer clock controlling circuit controls the buffer clock generating circuit to transfer the internal clock signal as the second buffer clock signal to the data output buffer circuit. ### Claim 21 A NAND flash memory device comprising: an interface block which receives an external read enable signal during a read operation to output an internal clock signal; a buffer clock controlling circuit which activates a clock enable signal in response to a first high-to-low transition of the internal clock signal when a data output enable signal is activated; a first clock generator which generates a first buffer clock signal in response to the clock enable signal and a lock flag signal which indicates whether a first clock signal has zero phase difference with respect to the internal clock signal; a second clock generator which generates a second buffer clock signal in response to the data output enable signal, the internal clock signal, and the lock flag signal; a selection circuit which selects one of the first buffer clock signal and the second buffer clock signal according to a control output of the buffer clock controlling circuit; and a data output buffer circuit which sequentially outputs read data in response to the buffer clock signal selected by the selection circuit, wherein the second buffer clock generating circuit generates the second buffer clock signal having a single pulse when the data output enable signal is activated, and wherein the first buffer clock generating circuit generates the first buffer clock signal having zero phase difference with respect to the internal clock signal after the external read enable signal is inputted, and a burst read latency time has passed. ### Claim 22 (depends on 21) The NAND flash memory device of claim 21, wherein the buffer clock controlling circuit controls the selection circuit to transfer the second buffer clock signal having a single pulse to the data output buffer circuit before the lock flag signal is generated. ### Claim 23 (depends on 21) The NAND flash memory device of claim 21, wherein the buffer clock controlling circuit controls the selection circuit to transfer the first buffer clock signal to the data output buffer circuit when the lock flag signal is generated. ### Claim 24 (depends on 21) The NAND flash memory device of claim 21, wherein the buffer clock controlling circuit controls the selection circuit to transfer the internal clock signal as the second buffer clock signal to the data output buffer circuit after the burst latency time passed and the lock flag signal is not generated. ### Claim 25 (depends on 21) The NAND flash memory device of claim 21, wherein the buffer clock controlling circuit deactivates the clock enable signal to deactivate the first buffer clock generator when the lock flag signal is not generated. ### Claim 26 (depends on 21) The NAND flash memory device of claim 21, wherein the burst read latency time is varied by changing an activation time of the clock enable signal. ### Claim 27 (depends on 21) The NAND flash memory device of claim 21, wherein the first buffer clock generating circuit includes a delay synchronization loop circuit. ### Claim 28 (depends on 21) The NAND flash memory device of claim 21, wherein the buffer clock controlling circuit generates a count-up controlling signal in response to the first high-to-low transition of the internal clock signal after the clock enable signal is activated. ### Claim 29 (depends on 28) The NAND flash memory device of claim 28, further comprising an address counter which receives an external address during the read operation to sequentially generate one or more internal addresses, wherein the address counter is synchronized with the internal clock signal to sequentially generate the one or more internal addresses when the count-up controlling signal is activated. ### Claim 30 (depends on 29) The NAND flash memory device of claim 29, further comprising: a page buffer circuit which reads from a memory cell array; and a column selection circuit which selects the page data of the page buffer circuit by a predetermined unit in response to an internal address outputted from the address counter and outputs the selected data as read data to the data output buffer circuit.