# US 7,609,552 B2 · Non-volatile memory with background data latch caching during erase operations

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,609,552 B2
- Document ID: US7609552B2
- Status: Granted
- Kind: B2
- Application number: 11/381,998
- Filed: 2006-05-05
- Published: 2006-10-19
- Granted: 2009-10-27
- Earliest claimed: 2005-04-01
- Assignees: SanDisk Corporation
- Inventors: Yan Li; Jason Lin
- Web page: https://patentgrep.com/patent/US7609552B2

## CPC

- G11C 16/26: Sensing or reading circuits; Data output circuits
- G06F 12/0893: Caches characterised by their organisation or structure
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 16/04: using variable threshold transistors, e.g. FAMOS
- G06F 2212/2022: Flash memory
- G06F 2212/3042: being part of a memory device, e.g. cache DRAM
- G11C 2207/2245: Memory devices with an internal cache buffer
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with an erase operation. In the exemplary embodiment, a read operation is inserted just prior to the erase operation or one or more read operations are inserted during a soft programming phase of the erase operation. In this way, the read data could be output while the erase operation is taking place, thereby making use of otherwise waiting time.

## Claims

### Claim 1

A non-volatile memory device having addressable pages of memory cells, comprising:
a sense amplifier and a set of data latches for each memory cell of an addressed page, said set of data latches dedicated to the sense amplifier for latching data read from the memory cell and for referencing data to be programmed to the memory cell;
a state machine for controlling an erase memory operation on a designated group of pages; and
for performing operations on the set of data latches with data related to one or more subsequent memory operations on the memory array, wherein said operations are performed contemporaneously with the erase operation.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the state machine controls the erase operation to remove charges stored in the memory cells of the designated group of pages.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the state machine controls the erase operation in a first phase, to remove charges stored in the memory cells of the designated group of pages until the memory cells have a threshold voltage below that of a predetermined ground state and
in a second phase to program the memory cells of the designated group of pages substantially to the predetermined ground state.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein the second phase further comprises:
said state machine controlling alternately applying a programming pulse to and verifying each of the memory cells of the designated group until each has been programmed to the predetermined ground state.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the memory cells each stores one bit of data.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the memory cells each stores more than one bit of data.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the one or more subsequent memory operations include one or more program operations.

### Claim 8 (depends on 7)

The memory device of claim 7, wherein the memory cells each stores one bit of data.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein the state machine controls operations on the set of data latches that include loading a page of binary program data thereto.

### Claim 10 (depends on 8)

The memory device of claim 8, wherein the state machine controls operations on the set of data latches that include loading more than one page of binary program data thereto.

### Claim 11 (depends on 7)

The memory device of claim 7, wherein the memory cells each stores more than one bit of data.

### Claim 12 (depends on 11)

The memory device of claim 11, wherein the state machine controls operations on the set of data latches that include loading a page of binary program data thereto.

### Claim 13 (depends on 11)

The memory device of claim 11, wherein the state machine controls operations on the set of data latches that include loading more than one page of binary program data thereto.

### Claim 14 (depends on 3)

The memory device of claim 3, wherein the state machine controls the one or more subsequent memory operations that include one or more read operations.

### Claim 15 (depends on 14)

The memory device of claim 14, wherein the one or more read operations are inserted during the second phase.

### Claim 16 (depends on 14)

The memory device of claim 14, wherein the one or more read operations are inserted just prior to the first phase.

### Claim 17 (depends on 14)

The memory device of claim 14, wherein the one or more read operations are part of a read scrub operations where existing data stored in the memory cells are read periodically to check for any errors, and when errors are found the corrected data are reprogrammed.

### Claim 18

A non-volatile memory device having addressable pages of memory cells, comprising:
a sense amplifier and a set of data latches for each memory cell of an addressed page, said set of data latches dedicated to the sense amplifier for latching data read from the memory cell and for referencing data to be programmed to the memory cell;
means for controlling an erase memory operation on a designated group of pages; and
means for performing operations on the set of data latches with data related to one or more subsequent memory operations on the memory array, wherein said operations are performed contemporaneously with the erase operation.

### Claim 19 (depends on 14, 15, 16, 17, 18)

The memory device as in any one of claims 14-18, wherein the memory cells each stores one bit of data.

### Claim 20 (depends on 14, 15, 16, 17, 18)

The memory device as in any one of claims 14-18, wherein the memory cells each stores more than one bit of data.