# US 7,609,550 B2 · Compact virtual ground diffusion programmable ROM array architecture, system and method

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- Number: US 7,609,550 B2
- Document ID: US7609550B2
- Status: Granted
- Kind: B2
- Application number: 12/099,640
- Filed: 2008-04-08
- Published: 2008-09-04
- Granted: 2009-10-27
- Earliest claimed: 2006-03-21
- Assignees: Virage Logic Corporation
- Inventors: Amit Khanuja; Deepak Sabharwal
- Web page: https://patentgrep.com/patent/US7609550B2

## CPC

- H10B 20/00: Read-only memory [ROM] devices
- G11C 17/12: using field-effect devices
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array of rows columns. A shared source line is associated with a first pair of adjacent columns, the shared source line being maintained at a predetermined level, wherein source terminals of storage cells in the adjacent columns are electrically coupled to the shared source line. A shared bit line is associated with a second pair of adjacent columns, the shared bit line being maintained at the predetermined level, wherein drain terminals of storage cells in the adjacent columns are electrically coupled to the shared bit line.

## Claims

### Claim 1

A method of programming a Read-Only Memory (ROM) circuit having a plurality of storage cells organized as an array of rows and columns, said method comprising:
for a first subset of storage cells, providing a diffusion area between source and drain terminals of each predetermined storage cell of said first subset for programming a first logic value thereat;
for a second subset of storage cells, withholding said diffusion area between source and drain terminals of each predetermined storage cell of said second subset for programming a second logic value thereat; and
providing at least one of a source diffusion extension and a drain diffusion extension for said source and drain terminals respectively, of a particular storage cell of said second subset that is disposed on a particular column, if said particular storage cell having said second logic value is located next to another storage cell on said particular column having said second logic value.

### Claim 2 (depends on 1)

The method of programming a ROM circuit as set forth in claim 1, wherein said first logic value comprises a binary 0.

### Claim 3 (depends on 1)

The method of programming a ROM circuit as set forth in claim 1, wherein said second logic value comprises a binary 1.

### Claim 4 (depends on 1)

The method of programming a ROM circuit as set forth in claim 1, wherein said source diffusion extension of said particular storage cell is extended over a shared source line associated with said particular storage cell.

### Claim 5 (depends on 1)

The method of programming a ROM circuit as set forth in claim 1, wherein said drain diffusion extension of said particular storage cell is extended over a shared bit line associated with said particular storage cell.

### Claim 6 (depends on 1)

A Read-Only Memory (ROM) circuit produced by the method as set forth in claim 1.

### Claim 7

A system for programming a Read-Only Memory (ROM) circuit having a plurality of storage cells organized as an array of rows and columns, said system comprising:
means for providing a diffusion area between source and drain terminals of each predetermined storage cell of a first subset of storage cells, thereby programming a first logic value thereat;
means for withholding said diffusion area between source and drain terminals of each predetermined storage cell of a second subset of storage cells, thereby programming a second logic value thereat; and
means for providing at least one of a source diffusion extension and a drain diffusion extension for said source and drain terminals, respectively, of a particular storage cell of said second subset that is disposed on a particular column, if said particular storage cell having said second logic value is located next to another storage cell on said particular column having said second logic value.

### Claim 8 (depends on 7)

The system for programming a ROM circuit as set forth in claim 7, wherein said first logic value comprises a binary 0.

### Claim 9 (depends on 7)

The system for programming a ROM circuit as set forth in claim 7, wherein said second logic value comprises a binary 1.

### Claim 10 (depends on 7)

The system for programming a ROM circuit as set forth in claim 7, wherein said source diffusion extension of said particular storage cell is extended over a shared source line associated with said particular storage cell.

### Claim 11 (depends on 7)

The system for programming a ROM circuit as set forth in claim 7, wherein said drain diffusion extension of said particular storage cell is extended over a shared bit line associated with said particular storage cell.