# US 7,609,549 B2 · Non-volatile multilevel memory cell programming > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,609,549 B2 - Document ID: US7609549B2 - Status: Granted - Kind: B2 - Application number: 12/346,353 - Filed: 2008-12-30 - Published: 2009-04-30 - Granted: 2009-10-27 - Earliest claimed: 2006-12-28 - Assignees: Micron Technology, Inc. - Inventors: Seiichi Aritome - Web page: https://patentgrep.com/patent/US7609549B2 ## CPC - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/12: Programming voltage switching circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number of threshold voltage ranges. One method includes programming a lower page of a first wordline cell to increase a threshold voltage (Vt) of the first wordline cell to a first Vt within a lowermost Vt range. The method includes programming a lower page of a second wordline cell prior to programming an upper page of the first wordline cell. The method includes programming the upper page of the first wordline cell such that the first Vt is increased to a second Vt, wherein the second Vt is within a Vt range which is then a lowermost Vt range and is positive. ## Claims ### Claim 1 A memory device comprising: an array of multilevel memory cells; and control circuitry coupled to the array and configured to: perform a first lower page programming process on a number of cells coupled to a particular wordline, wherein the lower page programming process increases a threshold voltage (Vt) of each of the number of cells from a negative Vt to one of a first number of Vt levels each corresponding to a number of different data states; subsequently perform an upper page programming process on the number of cells, wherein the upper page programming process programs the number of cells to a particular one of the number of different data states, and wherein each of the Vts corresponding to each of the number of different data states are positive Vts. ### Claim 2 (depends on 1) The device of claim 1, wherein the control circuitry is configured to perform at least a second and a third lower page programming process on the number of cells prior to performing the upper page programming process. ### Claim 3 (depends on 2) The device of claim 2, wherein the second lower page programming process adjusts the Vt of each of the number of cells from the one of the first number of Vt levels to one of a second number of Vt levels. ### Claim 4 (depends on 3) The device of claim 3, wherein the third lower page programming process adjusts the Vt of each of the number of cells from the one of the second number of Vt levels to one of a third number of Vt levels. ### Claim 5 (depends on 4) The device of claim 4, wherein each of the third number of Vt levels corresponds to two of the number of different data states. ### Claim 6 (depends on 5) The device of claim 5, wherein the two of the number of different data states are adjacent data states. ### Claim 7 A memory device comprising: an array of multilevel memory cells having a number of lower pages and an upper page of data associated therewith; and control circuitry coupled to the array and configured to: program a first lower page of a first group of cells of a first wordline, wherein each of the cells has an initial negative threshold voltage level corresponding to an erase state; subsequently program a second and a third lower page and an upper page of the cells of the first group, wherein at least one of the first, second, and third lower page and the upper page programming includes: applying a number of programming voltage pulses to a control gate of each of the cells of the first group until each of the cells of the first group has reached a positive threshold voltage (Vt) level of a number of positive Vt levels each corresponding to a different data state. ### Claim 8 (depends on 7) The device of claim 7, including verifying that each of the cells of the first group has reached the positive Vt level by applying a verify voltage of at least 0 volts to the control gate. ### Claim 9 (depends on 7) The device of claim 7, wherein the device is a NAND array of multilevel memory cells each programmed from an initial Vt level not greater than 0 volts to one of at least sixteen different Vt levels not less than 0, each of the sixteen different Vt levels corresponding to a respective different data state. ### Claim 10 (depends on 7) The device of claim 7, wherein the first wordline is adjacent to a source line of the array, and wherein the control circuitry is configured to program a first lower page of cells on at least a first next adjacent wordline, a second next adjacent wordline, and a third next adjacent wordline prior to programming the upper page of the first group of first wordline cells. ### Claim 11 (depends on 10) The device of claim 10, wherein the control circuitry is configured to program a second lower page of cells on at least the first next adjacent wordline and the second next adjacent wordline prior to programming the upper page of the first group of first wordline cells. ### Claim 12 (depends on 11) The device of claim 11, wherein the control circuitry is configured to program a third lower page of cells on at least the first next adjacent wordline prior to programming the upper page of the first group of first wordline cells. ### Claim 13 A method for programming an array of non-volatile multilevel memory cells to a number of different threshold voltage (Vt) levels corresponding to different data states, the method comprising: programming a lower page of a first wordline cell to increase a Vt of the first wordline cell to a first lowermost Vt level; programming a lower page of a second wordline cell prior to programming an upper page of the first wordline cell; and programming the upper page of the first wordline cell such that the Vt of the first wordline cell is increased to a second lowermost Vt level, wherein the second lowermost Vt level is positive. ### Claim 14 (depends on 13) The method of claim 13, wherein programming the lower page of the first wordline cell includes increasing the Vt of the first wordline cell from a negative Vt to the first lowermost Vt level. ### Claim 15 (depends on 13) The method of claim 13, wherein programming the lower page of the first wordline cell includes performing a compaction verify operation on the first wordline cell when a verify voltage associated with the first lowermost Vt level is not greater than zero volts. ### Claim 16 (depends on 15) The method of claim 15, wherein programming the lower page of the first wordline cell includes performing a program verify operation on the first wordline cell when the verify voltage associated with the first lowermost Vt level is at least zero volts. ### Claim 17 (depends on 15) The method of claim 15, wherein programming the upper page of the first wordline cell includes performing a program verify operation on the first wordline cell when the second lowermost Vt level is at least zero volts. ### Claim 18 (depends on 13) The method of claim 13, wherein the method includes programming a second lower page and a third lower page of the first wordline cell prior to programming the upper page of the first wordline cell. ### Claim 19 (depends on 18) The method of claim 18, wherein each of the non-volatile multilevel memory cells stores at least four bits of data. ### Claim 20 (depends on 13) The method of claim 13, wherein the method includes programming a lower page of a second first wordline cell after programming the lower page of the first wordline cell and prior to programming the upper page of the first wordline cell to the second lowermost Vt level.