# US 7,609,540 B2 · Serial bus controller using nonvolatile ferroelectric memory

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- Number: US 7,609,540 B2
- Document ID: US7609540B2
- Status: Granted
- Kind: B2
- Application number: 11/826,217
- Filed: 2007-07-13
- Published: 2007-11-15
- Granted: 2009-10-27
- Earliest claimed: 2003-01-24
- Assignees: Hynix Semiconductor Inc.
- Inventors: Hee Bok Kang
- Web page: https://patentgrep.com/patent/US7609540B2

## CPC

- G11C 11/22: using ferroelectric elements
- G06F 13/4291: {using a clocked protocol}
- G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits}
- G11C 7/24: Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
- G11C 29/02: Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C 29/022: {in I/O circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/50012: {of timing}
- G11C 2207/107: Serial-parallel conversion of data or prefetch
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A serial bus controller using a nonvolatile ferroelectric memory is provided. The memory controller structure using a nonvolatile ferroelectric register enables control of variable access time according to addresses when data are exchanged through a serial bus. In the serial bus controller according to an embodiment of the present invention, access latency time by addresses is programmed using a nonvolatile ferroelectric register, and address access time is differently controlled depending on the programmed access latency when data are exchanged between a master and a FRAM chip through a serial bus, thereby improving system performance.

## Claims

### Claim 1

A serial bus controller using a nonvolatile ferroelectric memory, comprising:
a memory controller for programming a code to control access latency time differently according to kinds of address in a nonvolatile ferroelectric memory and outputting a response signal to confirm completion of transmission of serial data/address when the serial data/address are transmitted in response to serial clock signals received through a serial bus; and
a FRAM chip for performing read/write operations of the memory during a pulse interval of the response signal,
wherein the memory controller controls the pulse interval of the response signal with a first cycle when a row address is transmitted, and controls the pulse interval of the response signal with a second cycle shorter than the first cycle when a column address is transmitted.

### Claim 2 (depends on 1)

The serial bus controller according to claim 1, wherein the memory controller controls the pulse interval of the response signal with the first cycle in a restore interval of the FRAM chip.

### Claim 3 (depends on 1)

The serial bus controller according to claim 1, wherein the FRAM chip comprises:
a sense amplifier buffer unit for amplifying data applied from a plurality of cell array blocks;
a data bus unit for exchanging inter-data between the plurality of cell array blocks and the sense amplifier buffer unit;
a data input/output buffer unit for buffering data inputted/outputted in the data bus unit;
a parallel/serial conversion controller for interconverting serial data inputted corresponding to serial clock signals with parallel data applied from the data input/output buffer unit; and
a write protecting controller for preventing data from being written in a corresponding sector of the plurality of cell array blocks when a write protecting command is set.

### Claim 4 (depends on 3)

The serial bus controller according to claim 3, wherein the parallel/serial conversion controller comprises:
a counter for counting a corresponding address when consecutive address/data are transmitted in a burst mode; and
a parallel/serial conversion unit for interconverting the serial data with the parallel data.