# US 7,609,500 B2 · Universal energy conditioning interposer with circuit architecture

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- Number: US 7,609,500 B2
- Document ID: US7609500B2
- Status: Granted
- Kind: B2
- Application number: 11/828,522
- Filed: 2007-07-26
- Published: 2008-07-03
- Granted: 2009-10-27
- Earliest claimed: 1997-04-08
- Assignees: X2Y Attenuators, LLC
- Inventors: Anthony A. Anthony; William M. Anthony
- Web page: https://patentgrep.com/patent/US7609500B2

## CPC

- H10W 70/685: comprising multiple insulating layers
- H05K 1/023: {using auxiliary mounted passive components or auxiliary substances (printed passive components H05K1/16)}
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/00: Interconnections or connectors in packages
- H05K 1/0237: {High frequency adaptations (H05K1/0216 takes precedence)}
- H05K 2201/09236: Parallel layout
- H05K 2201/10378: Interposers
- H10W 72/90: Bond pads, in general
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/728: {between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors}
- Y10T 29/49124: On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T 29/4913: Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T 29/49204: Contact or terminal manufacturing
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging. The invention can be employed between an active electronic component and a multilayer circuit card. A method for making the interposer is not presented and can be varied to the individual or proprietary construction methodologies that exist or will be developed.

## Claims

### Claim 1

A structure for conditioning power provided to an integrated circuit, comprising:
a power plane having a power plane surface and a power plane periphery;
a first ground plane having a first ground plane surface and a first ground plane periphery;
said power plane opposes said first ground plane;
said power plane couples power to signals of an integrated circuit;
said first ground plane couples ground to said signals;
said first ground plane is separated from said power plane by a first distance;
said first ground plane surface is larger than said power plane surface;
said first ground plane periphery extends a second distance from said power plane periphery;
said second distance is larger than said first distance; and
surfaces of said power plane define a plurality of vias extending through said power plane.

### Claim 2 (depends on 1)

The structure of claim 1 wherein said second distance is less than 20 times said first distance.

### Claim 3 (depends on 1)

The structure of claim 1 further comprising:
a second ground plane having a second ground plane surface and a second ground plane periphery;
said first ground plane and said second ground plane sandwich said power plane there between;
said second ground plane is separated from said power plane by a third distance;
said second ground plane surface is larger than said power plane surface;
said second ground plane periphery extends a fourth distance from said power plane periphery; and
said fourth distance is larger than said third distance.

### Claim 4 (depends on 1)

The structure of claim 1 further comprising a second ground plane, a third ground plane, and an additional power plane, such that the power and ground planes are stacked in the sequence: first ground plane; power plane; second ground plane; additional power plane; then third ground plane.

### Claim 5 (depends on 1)

The structure of claim 1 wherein said plurality of vias contain electrically conductive filling material that conductively connects said first ground plane to a second ground plane.

### Claim 6 (depends on 5)

The structure of claim 5 wherein said electrically conductive filling material contacts one of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins.

### Claim 7 (depends on 1)

The structure of claim 1 further comprising a contact array that conductively connects to at least said first ground plane and said power plane.

### Claim 8 (depends on 7)

The structure of claim 7 wherein said contact array comprises one of a C4 bump array, a BGA ball array, and a FCPGA pin array.

### Claim 9 (depends on 8)

The structure of claim 8 wherein said first ground plane has a plurality of adjacent contacts, the adjacent contacts being ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins.

### Claim 10

A structure for conditioning power provided to an integrated circuit, comprising:
a power plane having a power plane surface and a power plane periphery;
a first ground plane having a first ground plane surface and a first ground plane periphery;
a second ground plane having a second ground plane surface and a second ground plane periphery;
said first ground plane and said second ground plane sandwich said power plane there between;
said power plane couples power to signals of an integrated circuit;
said first ground plane couples ground to said signals;
said first ground plane is separated from said power plane by a first distance;
said first ground plane surface is larger than said power plane surface;
said first ground plane periphery extends a second distance from said power plane periphery;
said second distance is larger than said first distance
said second ground plane is separated from said power plane by a third distance;
said second ground plane surface is larger than said power plane surface;
said second ground plane periphery extends a fourth distance from said power plane periphery; and
said fourth distance is larger than said third distance.

### Claim 11 (depends on 10)

The structure of claim 10 wherein said second distance is less than 20 times said first distance.

### Claim 12 (depends on 10)

The structure of claim 10 further comprising a third ground plane and an additional power plane, such that the power and ground planes are stacked in the sequence: first ground plane; power plane; second ground plane; additional power plane; then third ground plane.

### Claim 13 (depends on 10)

The structure of claim 10 wherein at least one via contains electrically conductive filling material that conductively connects said first ground plane to said second ground plane.

### Claim 14 (depends on 13)

The structure of claim 13 wherein said electrically conductive filling material contacts one of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins.

### Claim 15 (depends on 1)

The structure of claim 1 further comprising a contact array that conductively connects to at least said first ground plane and said power plane.

### Claim 16 (depends on 15)

The structure of claim 15 wherein said contact array comprises one of a C4 bump array, a BGA ball array, and a FCPGA pin array.

### Claim 17 (depends on 15)

The structure of claim 15 wherein said first ground plane has a plurality of adjacent contacts, the adjacent contacts being ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins.

### Claim 18

A structure for conditioning power provided to signals of an integrated circuit, comprising:
a first conductive structure comprising a first planar common conductive region, a second planar common conductive region, and a third planar common conductive region;
a first power plane for coupling power to signals of said integrated circuit;
a second power plane for coupling power to signals of said integrated circuit;
said first power plane has a first power plane surface and a first power plane periphery;
said second power plane has a second power plane surface and a second power plane periphery;
said first planar common conductive region has a first planar common conductive region surface and a first planar common conductive region periphery;
said second planar common conductive region has a second planar common conductive region surface and a second planar common conductive region periphery;
said third planar common conductive region has a third planar common conductive region surface and a third planar common conductive region periphery;
said first planar common conductive region and said second planar common conductive region sandwich said first power plane there between;
said second planar common conductive region and said third planar common conductive region sandwich said second power plane there between;
surfaces of said first power plane define a plurality of vias extending through said first power plane;
said first planar common conductive region is separated from said first power plane by a first distance;
said first planar common conductive region surface is larger than a power plane surface;
said first planar common conductive region periphery extends a second distance from a power plane periphery; and
said second distance is larger than said first distance.

### Claim 19 (depends on 18)

The structure of claim 18 wherein vias extend through at least one of said first power plane and said second power plane.

### Claim 20 (depends on 18)

The structure of claim 18 further comprising a surface designed for mounting of said integrated circuit thereon.

### Claim 21 (depends on 20)

The structure of claim 20 wherein said surface includes at least one of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins.

### Claim 22 (depends on 1)

A packaged device comprising:
a die containing an integrated circuit;
a plurality of controlled collapse chip connection (C4) bumps attaching the die to a substrate; and
said structure of claim 1.

### Claim 23 (depends on 22)

The device of claim 22 wherein said second distance is less than 20 times said first distance.

### Claim 24 (depends on 22)

The device of claim 22 wherein said structure providing capacitance further comprises:
a second ground plane having a second ground plane surface and a second ground plane periphery;
said first ground plane and said second ground plane sandwiching said power plane there between;
said second ground plane separated from said power plane by a third distance;
said second ground plane surface is larger than said power plane surface;
said second ground plane periphery extends a fourth distance from said power plane periphery; and
said fourth distance is larger than said third distance.

### Claim 25 (depends on 24)

The device of claim 24 wherein said second ground plane is conductively connected to said first ground plane by conductive paths including electrically conductive filling material in said plurality of vias.

### Claim 26 (depends on 25)

The device of claim 25 further comprising a plurality of adjacent contacts, and wherein said plurality of vias electrical contact said plurality of adjacent contacts.

### Claim 27 (depends on 26)

The device of claim 26 wherein said plurality of adjacent contacts are ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins.

### Claim 28 (depends on 22)

The device of claim 22 wherein said structure providing capacitance further comprises a contact array that has contacts that conductively connects variously to the first ground plane and the power plane.

### Claim 29 (depends on 28)

The device of claim 28 wherein said contact array comprises at least one of a (C4) bump array, a BGA ball array, and a FCPGA pin array.

### Claim 30 (depends on 29)

The device of claim 29 wherein said first ground plane comprises a plurality of adjacent contacts comprising at least one of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins.

### Claim 31 (depends on 22)

The structure of claim 22 further comprising a second ground plane, a third ground plane, and an additional power plane, such that the power and ground planes are stacked in the sequence: first ground plane; power plane; second ground plane; additional power plane; then third ground plane.

### Claim 32

A method comprising:
coupling power to signals of an integrated circuit with a power plane having a power plane surface and a power plane periphery;
coupling ground to said signals with a first ground plane having a first ground plane surface and a first ground plane periphery;
said power plane opposes said first ground plane;
said first ground plane is separated from said power plane by a first distance;
said first ground plane surface is larger than said power plane surface;
said first ground plane periphery extends a second distance from said power plane periphery;
said second distance is larger than said first distance; and
surfaces of said power plane define a plurality of vias extending through said power plane.

### Claim 33

A combination of an energy conditioner and an integrated circuit, comprising;
a first pathway having a first surface and a first perimeter;
a second pathway having a second surface and a second perimeter;
said first pathway opposes said second pathway;
said first pathway is coupled to said integrated circuit;
said second pathway is coupled to said integrated circuit;
said second pathway is separated from said first pathway by a first distance;
said second surface larger than said first surface;
said second perimeter extends a second distance from said first perimeter;
said second distance is larger than said first distance; and
surfaces of said second pathway define a plurality of vias extending through said second pathway.

### Claim 34 (depends on 33)

The conditioner of claim 33 wherein said second pathway forms a portion of a conductive path from a source of power to said integrated circuit.

### Claim 35 (depends on 32)

The structure of claim 32 further comprising a third pathway, a fourth pathway, and a fifth pathway;
wherein said second pathway and said fourth pathway couple a source of power to said integrated circuit;
said first pathway, said third pathway, and said fifth pathway are conductively connected to one another and conductively isolated from said second pathway and said fourth pathway; and
said first pathway, said third pathway, and said fifth pathway from a conductive structure that separates said second pathway from said fourth pathway and that opposes the major surfaces of said second pathway and said fourth pathway.

### Claim 36

An enclosure comprising:
a power plane having a power plane surface and a power plane periphery, said power plane coupling power to signals of an integrated circuit; and
first and second ground planes having first and second ground plane surfaces and first and second ground plane peripheries, said first and second ground planes coupling ground to said signals;
said first and second ground planes are each separated from said power plane by no more than a first distance;
said first and second ground plane surfaces are larger than said power plane surface; and
said first and second ground plane peripheries extend from said power plane periphery by at least a second distance;
said second distance is greater than said first distance; and
at least one via that passes through said power plane.

### Claim 37 (depends on 36)

The enclosure of claim 36 wherein said first and second ground planes are conductively connected to one another by conductive paths formed at least partially in a plurality of vias that pass through said power plane.

### Claim 38 (depends on 37)

The enclosure of claim 37 wherein said plurality of vias contact a plurality of adjacent contacts.

### Claim 39 (depends on 38)

The enclosure of claim 38 wherein a plurality of adjacent contacts are ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins.

### Claim 40 (depends on 39)

The enclosure of claim 39 further comprises a contact array to connect to at least the first ground plane and the power plane.

### Claim 41 (depends on 40)

The enclosure of claim 40 wherein said contact array comprises at least one of a C4 bump array, a BGA ball array, and a FCPGA pin array.

### Claim 42 (depends on 36)

A packaged device comprising:
a die containing an integrated circuit;
a plurality of controlled collapse chip connection (C4) bumps attaching said die to a substrate; and
an enclosure of claim 36 attached to said die.

### Claim 43

A structure for conditioning power provided to an integrated circuit, comprising:
a first differential electrode having a first differential electrode surface and a first differential electrode periphery;
a shielding structure defining a first conductive layer, said first conductive layer having a first conductive layer surface and a first conductive layer periphery;
said first differential electrode opposes said first conductive layer;
said first differential electrode conductively connected to a conductive path between a source of electrical power and said integrated circuit;
said first conductive layer is separated from said first differential electrode by a first distance;
said first conductive layer surface is larger than said first differential electrode surface;
said first conductive layer periphery extends a second distance from said first differential electrode periphery;
said second distance is larger than said first distance; and
said surface of said first differential electrode defines a plurality of vias extending through said first differential electrode.

### Claim 44 (depends on 43)

The structure of claim 43 wherein said first conductive layer is conductively connected to a return pathway from said integrated circuit to said source of electrical power.

### Claim 45 (depends on 43)

The structure of claim 43 wherein said first conductive layer is not conductively connected to said integrated circuit.

### Claim 46

A structure for conditioning energy provided to an integrated circuit, comprising:
a first differential conductive layer having a first differential conductive layer surface area and a first differential conductive layer periphery;
a shielding structure defining a first conductive layer and a second conductive layer;
said first conductive layer having a first conductive layer surface area and a first conductive layer periphery;
said second conductive layer having a second conductive layer surface area and a second conductive layer periphery;
said first conductive layer and said second conductive layer sandwich said first differential conductive layer there between;
said first differential conductive layer couples energy to said integrated circuit;
said first conductive layer is separated from said first differential conductive layer by a first vertical distance;
said first conductive layer surface area is larger than said first differential conductive layer surface area;
said first conductive layer periphery extends a first horizontal distance from said first differential conductive layer periphery;
said first horizontal distance is larger than said first vertical distance
said second conductive layer is separated from said first differential conductive layer by a second vertical distance;
said second conductive layer surface area is larger than said first differential conductive layer surface area;
said second conductive layer periphery extends a second horizontal distance from said first differential conductive layer periphery; and
said second horizontal distance is larger than said second vertical distance.

### Claim 47 (depends on 45)

The structure of claim 45 further comprising a second differential conductive layer that is conductively isolated within said structure from said first differential conductive layer.

### Claim 48 (depends on 45)

The structure of claim 45 further comprising a second differential conductive layer that is conductively connected to said first differential conductive layer.

### Claim 49 (depends on 46)

The structure of claim 46 further comprising a second differential conductive layer, wherein said first differential conductive layer and said second differential conductive layer are conductively connected to one another.

### Claim 50 (depends on 46)

The structure of claim 46 further comprising a second differential conductive layer, wherein said first differential conductive layer and said second differential conductive layer are conductively isolated from said shielding structure.

### Claim 51 (depends on 48)

The structure of claim 48, wherein said first differential conductive layer and said second differential conductive layer are conductively isolated from said shielding structure.

### Claim 52 (depends on 43)

The structure of claim 43 further comprising a second conductive layer, wherein said first conductive layer and said second conductive layer are conductively connected to one another.

### Claim 53 (depends on 46)

The structure of claim 46 wherein said first conductive layer and said second conductive layer are conductively connected to one another.

### Claim 54 (depends on 47)

The structure of claim 47 wherein said first conductive layer and said second conductive layer are conductively connected to one another.

### Claim 55 (depends on 52)

The structure of claim 52 further comprising a third conductive layer, and wherein said first conductive layer, said second conductive layer and said third conductive layer are all conductively connected to one another.

### Claim 56 (depends on 47)

The structure of claim 47 further comprising a second conductive layer and a third conductive layer, and wherein said first conductive layer, said second conductive layer and said third conductive layer are all conductively connected to one another.

### Claim 57 (depends on 50)

The structure of claim 50, wherein said first differential conductive layer and said second differential conductive layer are conductively isolated from one another.

### Claim 58 (depends on 50)

The structure of claim 50, wherein said shielding structure further defines a third conductive layer, and wherein said first differential conductive layer and said second differential conductive layer are conductively isolated from one another.

### Claim 59 (depends on 58)

The structure of claim 58, wherein any of said conductive layers of said shielding structure are conductively coupled to one another.

### Claim 60 (depends on 50)

The structure of claim 50, wherein said first horizontal distance and said second horizontal distance are substantially the same size.

### Claim 61 (depends on 50)

The structure of claim 50, wherein said first vertical distance and said second vertical distance are substantially the same.

### Claim 62 (depends on 60)

The structure of claim 60, wherein said first vertical distance and said second vertical distance are substantially the same.