# US 7,609,495 B2 · Electrostatic discharge (ESD) protection arrangement and ESD protection method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,609,495 B2 - Document ID: US7609495B2 - Status: Granted - Kind: B2 - Application number: 11/590,677 - Filed: 2006-10-31 - Published: 2008-05-01 - Granted: 2009-10-27 - Earliest claimed: 2006-10-31 - Assignees: Infineon Technologies AG - Inventors: Wolfgang Soldner; Harald Gossner - Web page: https://patentgrep.com/patent/US7609495B2 ## CPC - H03F 1/52: Circuit arrangements for protecting such amplifiers {(monitoring arrangements G01R31/28; increasing reliability in communication systems, e.g. using redundancy H04B1/74)} - H03F: AMPLIFIERS ## Abstract AN ESD protection arrangement is provided which comprises an ESD protection device coupled between a terminal pad of an integrated semiconductor circuit and a supply voltage rail and a compensation loop provided between the terminal pad and an internal circuit node of the ESD protection device. The compensation loop comprises a phase shifting element to provide a predetermined phase shift between an input voltage of the ESD protection device and a compensation voltage supplied to the internal circuit node of the ESD protection device. ## Claims ### Claim 1 An integrated semiconductor circuit, comprising: a first ESD protection device having an input node coupled to a terminal pad of the integrated semiconductor circuit and an output node coupled to a first supply voltage rail of the integrated semiconductor circuit, and a compensation loop coupled between the input node and an intermediate circuit node of the first ESD protection device to provide a compensation voltage to the intermediate circuit node, wherein the compensation loop comprises a phase shifting element with a negative phase shift to provide a predetermined phase shift between an input signal voltage at the input node of the first protection device and the compensation voltage. ### Claim 2 (depends on 1) The integrated semiconductor circuit according to claim 1, wherein an amplification of the compensation loop is in a range from 0.8 to 1.4. ### Claim 3 (depends on 2) The integrated semiconductor circuit according to claim 2, wherein the amplification of the compensation loop is substantially 1. ### Claim 4 (depends on 1) The integrated semiconductor circuit according to claim 1, wherein the compensation loop includes a compensation amplifier. ### Claim 5 (depends on 4) The integrated semiconductor circuit according to claim 4, wherein the compensation amplifier includes at least two stages. ### Claim 6 (depends on 1) The integrated semiconductor circuit according to claim 1, wherein the predetermined phase shift corresponds to less than 9 ps. ### Claim 7 (depends on 1) The integrated semiconductor circuit according to claim 1, wherein the predetermined phase shift corresponds to substantially zero. ### Claim 8 (depends on 1) The integrated semiconductor circuit according to claim 1, wherein the first ESD protection device comprises a series connection of two protection elements, and wherein the intermediate circuit node is located between the protection elements. ### Claim 9 (depends on 1) The integrated semiconductor circuit according to claim 1, wherein the first ESD protection device comprises a thyristor, and wherein the intermediate circuit node comprises a control terminal of the thyristor. ### Claim 10 (depends on 9) The integrated semiconductor circuit according to claim 9, wherein the first ESD protection device further comprises a diode coupled between the control terminal of the thyristor and a second supply voltage rail. ### Claim 11 (depends on 1) The integrated semiconductor circuit according to claim 1, comprising: a second ESD protection device coupled between the terminal pad and a second supply voltage rail of the integrated semiconductor circuit, wherein the compensation voltage is further supplied to an intermediate circuit node of the second ESD protection device. ### Claim 12 (depends on 11) The integrated semiconductor circuit according to claim 11, wherein the second ESD protection device comprises a series connection of two protection elements, and wherein the intermediate circuit node of the second ESD protection device is located between the protection elements. ### Claim 13 (depends on 12) The integrated semiconductor circuit according to claim 12, wherein the second ESD protection device comprises a thyristor, and wherein the intermediate circuit node of the second ESD protection device is a control terminal of the thyristor. ### Claim 14 (depends on 13) The integrated semiconductor circuit according to claim 13, wherein the ESD second protection device further comprises a diode coupled between the control terminal of the thyristor and the first supply voltage rail. ### Claim 15 (depends on 1) The integrated semiconductor circuit according to claim 1, wherein the phase shifting element includes an inductor. ### Claim 16 (depends on 1) The integrated semiconductor circuit according to claim 1, wherein the compensation loop further includes at least a portion of an input amplifier connected to the terminal pad. ### Claim 17 (depends on 1) The integrated semiconductor circuit according to claim 1, wherein the compensation loop comprises a compensation amplifier and an input signal of the compensation amplifier is derived from an internal signal of an input amplifier connected to the terminal pad. ### Claim 18 An integrated semiconductor circuit, comprising: a first ESD protection device having an input node coupled to a terminal pad of the integrated semiconductor circuit and an output node coupled to a first supply voltage rail of the integrated semiconductor circuit, a compensation loop coupled between the terminal pad and an intermediate circuit node of the first ESD protection device to provide a compensation voltage to the intermediate circuit node, and a phase shifting element with a positive phase shift coupled between the terminal pad and the input node of the first ESD protection device so as to provide a predetermined phase shift between an input signal voltage at the input node of the first ESD protection device and the compensation voltage. ### Claim 19 (depends on 18) The integrated semiconductor circuit according to claim 18, wherein the compensation loop comprises a compensation amplifier. ### Claim 20 (depends on 18) The integrated semiconductor circuit according to claim 18, wherein an amplification of the compensation loop is in a range from 0.8 to 1.4. ### Claim 21 (depends on 20) The integrated semiconductor circuit according to claim 20, wherein the amplification of the compensation loop is substantially 1. ### Claim 22 (depends on 18) The integrated semiconductor circuit according to claim 18, wherein the predetermined phase shift corresponds to less than 9 ps. ### Claim 23 (depends on 18) The integrated semiconductor circuit according to claim 18, wherein the predetermined phase shift corresponds to substantially zero. ### Claim 24 (depends on 18) The integrated semiconductor circuit according to claim 18, wherein the phase shifting element includes a delay line. ### Claim 25 An ESD protection method, comprising: providing an ESD protection device having an input node coupled to a terminal pad of an integrated semiconductor circuit and an output node coupled to a supply voltage rail of the integrated semiconductor circuit, providing a compensation loop between the input node and an intermediate circuit node of the ESD protection device, providing a delay element with a negative phase shift in the compensation loop so as to adjust a predetermined phase shift between an input signal voltage at the input node of the ESD protection device and the compensation voltage. ### Claim 26 (depends on 25) The ESD protection method according to claim 25, comprising: adjusting an amplification of the compensation loop in a range from 0.8 to 1.4. ### Claim 27 (depends on 26) The ESD protection method according to claim 26, wherein the amplification is adjusted to substantially 1. ### Claim 28 (depends on 25) The ESD protection method according to claim 25, wherein the predetermined phase shift is adjusted to correspond to less than 9 ps. ### Claim 29 (depends on 25) The ESD protection method according to claim 25, wherein the predetermined phase shift is adjusted to correspond to substantially zero. ### Claim 30 (depends on 25) The ESD protection method according to claim 25, wherein the predetermined phase shift is adjusted depending on external components to be connected to the terminal pad. ### Claim 31 An ESD protection method, comprising: providing an ESD protection device having an input node coupled to a terminal pad of an integrated semiconductor circuit and an output node coupled to a supply voltage rail of the integrated semiconductor circuit, providing a compensation loop between the terminal pad and an intermediate circuit node of the ESD protection device, coupling a delay element with a positive phase shift between the terminal pad and the input node of the ESD protection device so as to adjust a predetermined phase shift between an input signal voltage at the input node of the ESD protection device and the compensation voltage. ### Claim 32 (depends on 31) The ESD protection method according to claim 31, comprising: adjusting an amplification of the compensation loop in a range from 0.8 to 1.4. ### Claim 33 (depends on 32) The ESD protection method according to claim 32, wherein the amplification is adjusted to substantially 1. ### Claim 34 (depends on 31) The ESD protection method according to claim 31, wherein the predetermined phase shift is adjusted to correspond to less than 9 ps. ### Claim 35 (depends on 31) The ESD protection method according to claim 31, wherein the predetermined phase shift is adjusted to correspond to substantially zero. ### Claim 36 (depends on 31) The ESD protection method according to claim 31, wherein the predetermined phase shift is adjusted depending on external components to be connected to the terminal pad.