# US 7,609,405 B2 · Central processor integrated circuitry for a print controller of a pagewidth printhead

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- Number: US 7,609,405 B2
- Document ID: US7609405B2
- Status: Granted
- Kind: B2
- Application number: 11/330,061
- Filed: 2006-01-12
- Published: 2006-06-08
- Granted: 2009-10-27
- Earliest claimed: 1998-12-16
- Assignees: Silverbrook Research Pty Ltd
- Inventors: Kia Silverbrook
- Web page: https://patentgrep.com/patent/US7609405B2

## CPC

- B41J 2/01: Ink jet
- B41J 2/00: Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed (mounting, arrangement or disposition of types or dies B41J1/00)
- B41J 2/0057: {where an intermediate transfer member receives the ink before transferring it on the printing material}
- B41J 2/04528: {aiming at warming up the head}
- B41J 2/04543: {Block driving}
- B41J 2/04551: {using several operating modes}
- B41J 2/04563: {detecting head temperature; Ink temperature}
- B41J 2/04586: {controlling heads of a type not covered by groups B41J2/04575 - B41J2/04585, or of an undefined type}
- B41J 2/04591: {Width of the driving signal being adjusted}
- B41J 2/155: for line printing
- B41J 2/165: Prevention {or detection} of nozzle clogging, e.g. cleaning, capping or moistening for nozzles
- B41J 2/16508: {connected with the printer frame}
- B41J 3/445: {Printers integrated in other types of apparatus, e.g. printers integrated in cameras}
- B41J 3/60: for printing on both faces of the printing material
- B41J 11/0095: {Detecting means for copy material, e.g. for detecting or sensing presence of copy material or its leading or trailing end}
- B41J 11/42: Controlling {printing material conveyance for accurate alignment of the printing material with the printhead; Print registering}
- B41J 13/076: Construction of rollers; Bearings therefor
- B41J 13/103: {for the sheet feeding section}
- B41J 19/202: {Drive control means for carriage movement}
- B41J 29/023: {with reduced dimensions}
- B41J 29/04: Means for attaching machines to baseboards
- B41J 29/17: Cleaning arrangements
- B41J 29/38: Drives, motors, controls or automatic cut-off devices for the entire printing mechanism
- G03G 15/10: using a liquid developer
- G03G 15/50: {Machine control of apparatus for electrographic processes using a charge pattern, e.g. regulating differents parts of the machine, multimode copiers, microprocessor control (sequencing control G03G21/14)}
- G03G 15/6529: {Transporting (G03G15/6555 takes precedence)}
- G06F 3/12: Digital output to print unit {, e.g. line printer, chain printer}
- G06F 13/00: Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor G06F9/46}; multiprocessor systems G06F15/16 )
- G06F 15/00: Digital computers in general (details G06F1/00 – G06F13/00); Data processing equipment in general
- G06K 1/00: Methods or arrangements for marking the record carrier in digital fashion
- G06K 15/02: using printers
- G06K 15/102: {using ink jet print heads}
- G06K 15/16: Means for paper feeding or form feeding
- G06K 15/1814: {including print-ready data, i.e. data already matched to the printing process}
- G06K 15/1815: {Receiving print data in mixed format}
- H04N 1/23: Reproducing arrangements
- H04N 1/32561: {using a programmed control device, e.g. a microprocessor}
- H04N 1/32587: {Controller}
- H04N 1/32593: {Using a plurality of controllers, e.g. for controlling different interfaces}
- H04N 1/32603: {Multi-bus systems}
- H04N 1/41: Bandwidth or redundancy reduction (by scanning H04N1/17 {; methods or arrangements for coding, decoding, compressing or decompressing digital video signals H04N19/00})
- H04N 1/504: {Reproducing the colour component signals line-sequentially}
- G03G 2221/1642: for the transfer unit
- B41J: TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- G03G: ELECTROGRAPHY; ELECTROPHOTOGRAPHY; MAGNETOGRAPHY
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06K: GRAPHICAL DATA READING (image or video recognition or understanding G06V); PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

A central processor integrated circuit for a printer controller of a pagewidth inkjet printer includes a bus. Host interface circuitry is connected to the bus and is configured to receive compressed page data having a bi-level black layer and a contone color layer and to communicate the compressed page data to the bus. Black layer expansion circuitry is connected to the bus and is configured to receive and expand the bi-level black layer. Color layer expansion circuitry is connected to the bus and is configured to receive and expand the contone layer. Halftoner and compositor circuitry is connected to the bus and is configured to receive expanded bi-level black layer data and expanded contone layer data and to composite the bi-level black layer over the contone layer. Processor circuitry is connected to the bus and is programmed to control operation of components of the central processor integrated circuit. DMA controller circuitry is connected to the bus and is configured to be programmed by the processor circuitry to generate addresses for data transfer between the components. Printhead interface circuitry is connected to the bus to facilitate communication between the bus and a pagewidth printhead.

## Claims

### Claim 1

A central processor integrated circuit for a printer controller of a pagewidth inkjet printer, the integrated circuit comprising
a bus;
host interface circuitry connected to the bus and configured to receive compressed page data having a bi-level black layer and a contone color layer and to communicate the compressed page data to the bus;
black layer expansion circuitry connected to the bus and configured to receive and expand the bi-level black layer;
color layer expansion circuitry connected to the bus and configured to receive and expand the contone layer;
halftoner and compositor circuitry connected to the bus and configured to receive expanded bi-level black layer data and expanded contone layer data and to composite the bi-level black layer over the contone layer;
processor circuitry connected to the bus and programmed to control operation of components of the central processor integrated circuit;
DMA controller circuitry connected to the bus and configured to be programmed by the processor circuitry to generate addresses for data transfer between the components; and
printhead interface circuitry connected to the bus to facilitate communication between the bus and a pagewidth printhead.

### Claim 2 (depends on 1)

A central processor integrated circuit as claimed in claim 1, in which the black layer expansion circuitry is configured to expand the bi-level black layer in EDRL format.

### Claim 3 (depends on 1)

A central processor integrated circuit as claimed in claim 1, in which the black layer expansion circuitry is configured to expand the bi-level black layer in one of Group 3 and Group 4 facsimile compressed format.

### Claim 4 (depends on 1)

A central processor integrated circuit as claimed in claim 1, in which the color layer expansion circuitry is configured to define a JPEG decoder.

### Claim 5 (depends on 1)

A central processor integrated circuit as claimed in claim 1, in which the circuitry components connected to the bus each incorporate FIFO buffer circuitry, the DMA controller circuitry being multi-channelled and configured to allocate a channel for the FIFO buffer circuitry of each component and to handle single-address transfers and to provide a request/acknowledge interface for each channel.

### Claim 6 (depends on 5)

A central processor integrated circuit as claimed in claim 5, in which the DMA controller circuitry is configured to facilitate graceful stalling of the relevant circuitry components whenever an associated input buffer is empty or an associated output buffer is full.

### Claim 7 (depends on 1)

A central processor integrated circuit as claimed in claim 1, which includes at least one of parallel interface circuitry to facilitate communication between the bus and an operator interface, motors and sensors and serial interface circuitry to facilitate communication between quality assurance circuitry and the bus.