# US 7,609,329 B2 · Driving apparatus for liquid crystal display > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,609,329 B2 - Document ID: US7609329B2 - Status: Granted - Kind: B2 - Application number: 10/868,766 - Filed: 2004-06-17 - Published: 2004-12-23 - Granted: 2009-10-27 - Earliest claimed: 2003-06-21 - Assignees: LG Display Co., Ltd. - Inventors: Jong Sang Baek; Sun Young Kwon - Web page: https://patentgrep.com/patent/US7609329B2 ## CPC - G09G 5/18: Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12}) - G09G 2340/0478: Horizontal positioning - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A driving apparatus for a liquid crystal display capable of adjusting a field area displayed on a liquid crystal display panel at the exterior thereof is disclosed. In the apparatus, an image signal processor separates a television image signal from a complex image signal and separates a complex synchronizing signal. A liquid crystal display panel displays the television image signal. A timing controller generates a source start pulse determining a display start time of the television image signal displayed on the liquid crystal display panel using an internal clock signal and the complex synchronizing signal from the image signal processor. A delay circuit delays the internal clock signal to apply it to the timing controller. ## Claims ### Claim 1 A driving apparatus for a liquid crystal display, comprising: an image signal processor for separating a television image signal from a complex image signal and for separating a complex synchronizing signal; a liquid crystal display panel for displaying the television image signal; delay means electrically connected to a source start pulse generator of a timing controller for delaying one of a frequency-dividing clock signal and a horizontal synchronizing signal from the timing controller and supplying the delayed one to the source start pulse generator of the timing controller; and the source start pulse generator for generating a source start pulse determining a display start time of the television image signal displayed on the liquid crystal display panel using the delayed one from the delay means and the complex synchronizing signal from the image signal processor. ### Claim 2 (depends on 1) The driving apparatus as claimed in claim 1, further comprising: a data driver for applying the television image signal to data lines of the liquid crystal display panel in response to a first set of control signals from the timing controller, the first set of control signals including the source start pulse from the timing controller; and a gate driver for driving gate lines of the liquid crystal display panel in response to a second set of control signals from the timing controller. ### Claim 3 (depends on 1) The driving apparatus as claimed in claim 1, wherein the frequency-dividing clock signal has the same period as the complex synchronizing signal; and the horizontal synchronizing signal is inverted from the complex synchronizing signal. ### Claim 4 (depends on 3) The driving apparatus as claimed in claim 3, further comprising: a phase locked loop control circuit for applying a phase locked loop for synchronizing a rising edge of the frequency-dividing clock signal with a center portion of the width of the complex synchronizing signal to the timing controller. ### Claim 5 (depends on 1) The driving apparatus as claimed in claim 1, wherein the delay means includes: a variable resistor connected to an output terminal of the timing controller for outputting the frequency-dividing clock signal; and a capacitor connected between the variable resistor and a ground voltage source, wherein a node between the variable resistor and the capacitor is electrically connected to a clock input terminal of the source start pulse generator. ### Claim 6 (depends on 1) The driving apparatus as claimed in claim 1, wherein the delay means includes: a variable resistor connected to an output terminal of the timing controller for outputting the horizontal synchronizing signal; and a capacitor connected between the variable resistor and a ground voltage source, wherein a node between the variable resistor and the capacitor is connected to a clock input terminal of the source start pulse generator. ### Claim 7 A driving apparatus for a liquid crystal display, comprising: an image signal processor for separating a television image signal from a complex image signal and for separating a complex synchronizing signal; a liquid crystal display panel for displaying the television image signal; a variable circuit connected to a source start pulse generator of a timing controller for generating a variable signal delayed from one of a frequency-dividing clock signal and a horizontal synchronizing signal from the timing controller for adjusting a display start time of the television image signal displayed on the liquid crystal display panel by a user and supplying the delayed one to the source start pulse generator of the timing controller; the source start pulse generator for generating a source start pulse determining a display start time of the television image signal displayed on the liquid crystal display panel using the variable signal from variable circuit and the complex synchronizing signal; and a phase locked loop control circuit for generating a phase locked loop and applying the phase locked loop to the timing controller. ### Claim 8 (depends on 7) The driving apparatus as claimed in claim 7, further comprising: a data driver for applying the television image signal to data lines of the liquid crystal display panel in response to a first set of control signals from the timing controller, the first set of control signals including the source start pulse from the timing controller; and a gate driver for driving gate lines of the liquid crystal display panel in response to a second set of control signals from the timing controller. ### Claim 9 (depends on 7) The driving apparatus as claimed in claim 7, wherein the timing controller includes: a frequency divider for generating the one of a frequency-dividing clock signal and a horizontal synchronizing signal using the complex synchronizing signal. ### Claim 10 (depends on 9) The driving apparatus as claimed in claim 9, wherein the frequency-dividing clock signal has the same period as the complex synchronizing signal; and the horizontal synchronizing signal is inverted from the complex synchronizing signal. ### Claim 11 (depends on 10) The driving apparatus as claimed in claim 10, further comprising: a phase locked loop control circuit for applying a phase locked loop for synchronizing a rising edge of the frequency-dividing clock signal with a center portion of the width of the complex synchronizing signal to the timing controller. ### Claim 12 (depends on 10) The driving apparatus as claimed in claim 10, wherein the variable circuit delays the one of a frequency-dividing clock signal and a horizontal synchronizing signal from the frequency divider to generate a variable signal for varying the display start time, and applies the generated variable signal to the source start pulse generator. ### Claim 13 (depends on 12) The driving apparatus as claimed in claim 12, wherein the variable circuit includes: a variable resistor connected to an output terminal of the timing controller for outputting the frequency-dividing clock signal; and a capacitor connected between the variable resistor and a ground voltage source, wherein a node between the variable resistor and the capacitor is electrically connected to a clock input terminal of the source start pulse generator. ### Claim 14 (depends on 13) The driving apparatus as claimed in claim 13, wherein the variable resistor is adjusted by a user. ### Claim 15 (depends on 12) The driving apparatus as claimed in claim 12, wherein the variable circuit includes: a variable resistor connected to an output terminal of the timing controller for outputting the horizontal synchronizing signal; and a capacitor connected between the variable resistor and a ground voltage source, wherein a node between the variable resistor and the capacitor is electrically connected to a clock input terminal of the source start pulse generator. ### Claim 16 (depends on 15) The driving apparatus as claimed in claim 15, wherein the variable resistor is adjusted by a user. ### Claim 17 A flat panel display device, comprising: an image signal processor for separating a video image signal from a complex image signal and for separating a complex synchronizing signal; a display panel for displaying the video image signal; a variable circuit connected to a source start pulse generator of a timing controller for generating a variable signal delayed from one of a frequency-dividing clock signal and a horizontal synchronizing signal from the timing controller for adjusting a display start time of the video image signal displayed on the display panel by a user and supplying the delayed one to the source start pulse generator of the timing controller; the source start pulse generator for generating a source start pulse determining a display start time of the video image signal displayed on the display panel using the variable signal from variable circuit and the complex synchronizing signal; and a phase locked loop control circuit for generating a phase locked loop and applying the phase locked loop to the timing controller. ### Claim 18 (depends on 17) The flat panel display device as claimed in claim 17, wherein the timing controller includes: a frequency divider for generating the one of a frequency-dividing clock signal and a horizontal synchronizing signal using the complex synchronizing signal. ### Claim 19 (depends on 18) The flat panel display device as claimed in claim 18, wherein the frequency-dividing clock signal has the same period as the complex synchronizing signal; and the horizontal synchronizing signal is inverted from the complex synchronizing signal.