# US 7,609,194 B2 · Clock signal generating device and analog-digital conversion device

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- Number: US 7,609,194 B2
- Document ID: US7609194B2
- Status: Granted
- Kind: B2
- Application number: 11/964,943
- Filed: 2007-12-27
- Published: 2008-07-03
- Granted: 2009-10-27
- Earliest claimed: 2006-12-27
- Assignees: Panasonic Corporation
- Inventors: Yoshikazu Makabe; Ikuo Hidaka; Koji Oka; Toshiaki Ozeki
- Web page: https://patentgrep.com/patent/US7609194B2

## CPC

- H03M 1/0624: {by synchronisation}
- G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)}
- H03K 5/151: with two complementary outputs
- H03M 1/1215: {using time-division multiplexing}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A first Delayed Flip Flop includes a first D input terminal, a first clock input terminal, a first output terminal outputting a signal inputted to the first D input terminal based on the clock signal, and a first inversion output terminal inverting and outputting the signal inputted to the first D input terminal and outputting the signal to the first D input terminal as a feedback. A second Delayed Flip Flop includes a second D input terminal receiving the output from the first output terminal of the first Delayed Flip Flop, a second clock input terminal, and a second output terminal outputting the signal inputted to the second D input terminal as a first output based on the clock signal. A third Delayed Flip Flop includes a third D input terminal receiving the output from the first inversion output terminal of the first Delayed Flip Flop, a third clock input terminal, and a third output terminal outputting the signal inputted to the third D input terminal as a second output based on the clock signal. The first output and the second output have signal waveforms inverted at the same timing.

## Claims

### Claim 1

A clock signal generating device comprising first, second and third Delayed Flip Flops, wherein
the first Delayed Flip Flop comprises:
a first D input terminal;
a first clock input terminal operable to receive a clock signal;
a first output terminal operable to hold and output a signal inputted to the first D input terminal, based on the clock signal; and
a first inversion output terminal operable to invert and output the signal inputted to the first D input terminal and output the signal to the first D input terminal as a feedback, based on the clock signal,
the second Delayed Flip Flop comprises:
a second D input terminal operable to receive the output from the first output terminal of the first Delayed Flip Flop;
a second clock input terminal operable to receive the clock signal; and
a second output terminal operable to hold a signal inputted to the second D input terminal and output the signal as a first output, based on the clock signal,
the third Delayed Flip Flop comprises:
a third D input terminal operable to receive the output from the first inversion output terminal of the first Delayed Flip Flop;
a third clock input terminal operable to receive the clock signal; and
a third output terminal operable to hold a signal inputted to the third D input terminal and output the signal as a second output, based on the clock signal, and
wherein the first output from the second output terminal of the second Delayed Flip Flop and the second output from the third output terminal of the third Delayed Flip Flop have signal waveforms inverted at the same timing,
wherein non-inversion outputs of the second Delayed Flip Flop and the third Delayed Flip Flop are same in timing with respect to the clock signal.

### Claim 2 (depends on 1)

An IC chip, wherein
the clock signal generating device according to claim 1 is mounted thereon.

### Claim 3 (depends on 1)

An analog-digital conversion device comprising:
the clock signal generating device according to claim 1; and
an A/D converter operable to convert an inputted analog signal to a digital signal by switching a sampling period and a holding period, according to the first output and the second output having the mutually inverted signal waveforms, outputted from the clock signal generating device.

### Claim 4 (depends on 3)

The analog-digital conversion device according to claim 3, wherein
the A/D converter comprises:
an A channel-side converter operable to convert the inputted analog signal to a digital signal by switching a sampling period and a holding period on the A channel side, according to the first output from the clock signal generating device, and
a B channel-side converter operable to convert the inputted analog signal to a digital signal by switching a sampling period and a holding period on the B channel side, according to the second output from the clock signal generating device.

### Claim 5 (depends on 3)

An IC chip, wherein
the analog-digital conversion device according to claim 3 is mounted thereon.