# US 7,609,188 B2 · Multi-standard analog-to-digital data conversion > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,609,188 B2 - Document ID: US7609188B2 - Status: Granted - Kind: B2 - Application number: 11/944,174 - Filed: 2007-11-21 - Published: 2009-05-21 - Granted: 2009-10-27 - Earliest claimed: 2007-11-21 - Assignees: Infineon Technologies AG - Inventors: Antonio Di Giandomenico; David San Segundo Bello; Andreas Wiesbauer; Susana Paton Alvarez; Jorg Hauptmann - Web page: https://patentgrep.com/patent/US7609188B2 ## CPC - H03M 3/398: {among different converter types} - H03M 3/416: {all these quantisers being multiple bit quantisers} - H03M 3/454: {with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract Implementations related to multi-standard digital subscriber line analog-to-digital data conversion are described. ## Claims ### Claim 1 A circuit, comprising: at least first and second sigma delta converters for processing signals of multiple digital subscriber line (DSL) standards, wherein: in a first configuration the circuit processes signals of a first DSL standard utilizing either of the first and the second sigma delta converters; in a second configuration the circuit processes signals of a second DSL standard utilizing the first sigma delta converter cascaded into the second sigma delta converter; and in a third configuration the circuit is configured to bypass a set of components in the second sigma delta converter to process signals of a third DSL standard. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the set of components comprise a digital-to-analog converter and an analog filter that comprises an integrator, and a feedback element ### Claim 3 (depends on 1) The circuit of claim 1, wherein in the second configuration quantization noise of the first sigma delta converter is cascaded into the second sigma delta converter and a digital output of the circuit is derived from an output of the second sigma delta converter subtracted from an output of the first sigma delta converter. ### Claim 4 (depends on 1) The circuit of claim 1, wherein in relation to the second DSL standard the circuit is configured to bypass a set of components of the second sigma delta converter and subtract a digital output of the second sigma delta converter from a digital output of the first sigma delta converter to produce the circuit's digital output. ### Claim 5 (depends on 1) The circuit of claim 1, wherein each of the first and second sigma delta converters include a pair of serially arranged integrators, a feedback loop to form a resonator together with the integrators, and a clock input, and wherein the circuit can be tuned to a particular standard by adjusting a frequency of the clock input and coefficients of the respective integrators and resonator. ### Claim 6 (depends on 1) The circuit of claim 1, wherein each of the first and second sigma delta converters include a pair of integrators, a feedback loop, and a clock input, and wherein in relation to the first standard the second sigma delta converter is bypassed and the circuit is tuned by adjusting a frequency of the clock input and coefficients of the integrators and resonator of the first sigma delta converter and wherein in relation to the second standard quantization noise of the first sigma delta converter is cascaded to the second sigma delta converter and the circuit is tuned by adjusting a frequency of the clock input and coefficients of the integrators and resonator of both of the first and second sigma delta converters. ### Claim 7 (depends on 6) The circuit of claim 6, wherein in relation to a third standard quantization noise of the first sigma delta converter is fed to the second sigma delta converter where the feedback loop and one of the integrators is bypassed and the circuit is tuned by adjusting a frequency of the clock input and coefficients of the integrators and resonator of the first sigma delta converter and a frequency of the clock input and coefficient of the non-bypassed integrator of the second sigma delta converter. ### Claim 8 (depends on 1) The circuit of claim 1 embodied on a device comprising one of a DSL modem and a DSL exchange. ### Claim 9 A device, comprising: a circuit comprising at least first and second sigma delta converters for processing analog input signals selected from one of multiple digital subscriber line (x-DSL) standards, wherein to process at least one of the standards, the analog input signals are received at the first sigma delta converter and quantization noise from the first sigma delta converter is processed by the second sigma delta converter and wherein digital output of the circuit is derived by subtracting an output of the second sigma delta converter from an output of the first sigma delta converter; wherein each of the first and second sigma delta converters includes a pair of serially arranged integrators, a feedback loop, and a clock, and wherein the circuit can be tuned to a particular x-DSL analog input signal standard by adjusting a frequency of the clock and coefficients of the integrators and a resonator. ### Claim 10 (depends on 9) The device of claim 9, further comprising noise cancellation filters for cancelling noise in the output of the first and second sigma delta converters before the subtracting. ### Claim 11 (depends on 9) The device of claim 9, wherein the first sigma delta converter includes first and second serially arranged integrators for receiving the input signals and wherein the quantization noise is received at the second sigma delta converter as a difference between a first signal sampled from between the first and second integrators and a second signal sampled after the integrators. ### Claim 12 A method, comprising: identifying an input standard from multiple digital subscriber line (x-DSL) standards; and enabling standard specific components of a configurable multistage noise shaping (MASH) circuit to process analog input signals of the identified input standard, wherein: a first configuration of the MASH circuit processes signals of a first DSL standard utilizing either of a first and a second sigma delta converters, a second configuration of the MASH circuit processes signals of a second DSL standard utilizing the first sigma delta converter cascaded into the second sigma delta converter, and a third configuration the circuit bypasses a set of components in the second sigma delta converter to process signals of a third DSL standard. ### Claim 13 (depends on 12) The method according to claim 12, wherein the identifying comprises one or more of sampling the input signals to identify the standard, and receiving an indication that identifies the input standard. ### Claim 14 (depends on 12) The method according to claim 12, wherein the enabling comprises controlling one or more controllable switches that are electrically connected to the specific components according to computer readable programming instructions. ### Claim 15 (depends on 12) The method according to claim 12, wherein the enabling comprises enabling one or both of: a first stage of the configurable MASH circuit for processing input signals and a second stage of the configurable MASH circuit for processing quantization noise of the first stage. ### Claim 16 (depends on 12) The method according to claim 12, wherein the enabling for a first identified standard comprises enabling a first stage of the configurable MASH circuit for processing input signals to produce digital output corresponding to the analog input signals and not enabling a second stage of the configurable MASH circuit. ### Claim 17 (depends on 12) The method according to claim 12, wherein the enabling for a first identified standard comprises adjusting component specific processing coefficients corresponding to the identified input standard. ### Claim 18 A device, comprising: a circuit comprising at least first and second sigma delta converters for processing analog input signals selected from one of multiple communications standards, wherein: in a first configuration the circuit processes signals of a first DSL standard utilizing either of the first and the second sigma delta converters, in a second configuration the circuit processes signals of a second DSL standard utilizing the first sigma delta converter cascaded into the second sigma delta converter, and in a third configuration the circuit is configured to bypass a set of components in the second sigma delta converter to process signals of a third DSL standard. ### Claim 19 (depends on 18) The device according to claim 18, wherein to process at least one of the standards, the analog input signals are received at the first sigma delta converter and quantization noise from the first sigma delta converter is processed by the second sigma delta converter and wherein digital output of the circuit is derived by subtracting an output of the second sigma delta converter from an output of the first sigma delta converter.