# US 7,609,125 B2 · System, device and method for reducing cross-talk in differential signal conductor pairs > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,609,125 B2 - Document ID: US7609125B2 - Status: Granted - Kind: B2 - Application number: 11/580,444 - Filed: 2006-10-13 - Published: 2008-04-17 - Granted: 2009-10-27 - Earliest claimed: 2006-10-13 - Assignees: Avago Technologies Enterprise IP (Singapore) Pte. Ltd. - Inventors: Minh van Quach; Nurwati S. Devnani; Robert B. Manley - Web page: https://patentgrep.com/patent/US7609125B2 ## CPC - H05K 1/0219: {Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors} - H10W 44/20: at high-frequency [HF] or radio frequency [RF] - H05K 1/0237: {High frequency adaptations (H05K1/0216 takes precedence)} - H05K 2201/0715: provided by an outer layer of PCB - H05K 2201/09236: Parallel layout - H10W 44/216: {Waveguides, e.g. strip lines} - H10W 44/223: {Differential pair signal lines} - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Systems, devices and methods are disclosed herein for reducing crosstalk between pairs of differential signal conductors. One or more ground traces connected to one or more over- or under-lying ground planes by vias are located between pairs of differential signal conductors. The electrical shielding provided by the combination of the one or more ground traces and the one or more ground planes results in reduced cross-talk between different pairs of differential signal conductors, and facilitates high-speed data rates between integrated circuits and printed circuit boards. In a preferred embodiment, such ground traces and ground planes are employed in HiTCE packaging containing multiple pairs of differential signal conductors. ## Claims ### Claim 1 An integrated circuit package configured to reduce cross-talk and maintain constant impedance in first and second differential signal conductor pairs incorporated therein, comprising: (a) a substrate; (b) a first ground plane disposed below the substrate; (c) a second ground plane disposed above the substrate; (d) respective pairs of first and second differential signal conductors disposed within the substrate and substantially in a first plane; and (e) a third pair of victim conductors disposed within the substrate and substantially in the first plane, the third pair of victim conductors further being disposed between the first and second pairs of differential signal conductors; (f) at least first and second ground traces disposed in the substrate and substantially in the first plane, the first and second ground traces being disposed, respectively, between the first pair of differential signal conductors and the third pair of victim conductors, and between the second pair of differential signal conductors and the third pair of victim conductors, wherein the first and second ground traces are electrically connected to the first and second ground planes, and further wherein the widths of the first and second ground traces are varied along their respective routes within the substrate to maintain constant impedance in the first and second pairs of differential signal conductors. ### Claim 2 (depends on 1) The device of claim 1, wherein a spacing between the first and second pairs of differential signal conductors is constant. ### Claim 3 (depends on 1) The device of claim 1 wherein a spacing between the first and second pairs of differential signal conductors changes. ### Claim 4 (depends on 3) The device of claim 3, wherein the spacing changes to accommodate pitch differences. ### Claim 5 (depends on 4) The device of claim 4 wherein the pitch differences are associated with changes occurring between the integrated circuit package and a printed circuit board. ### Claim 6 (depends on 1) The device of claim 1, wherein at least one of the first pair of conductors and the second pair of conductors has a trace heights ranging between about 2 μm and about 100 μm, between about 4 μm and about 80 μm, between about 6 μm and about 40 μm, between about 8 μm and about 20 μm, and between about 10 μm and about 14 μm. ### Claim 7 (depends on 1) The device of claim 1, wherein the spacing between the first ground trace or the second ground trace and the first pair of conductors or the second pair of conductors ranges between about 10 μm and about 1000 μm, between about 20 μm and about 500 μm, between about 30 μm and about 250 μm, between about 40 μm and about 120 μm, or between about 60 μm and about 100 μm. ### Claim 8 (depends on 1) The device of claim 1, wherein the spacing between the first ground plane and the second ground plane ranges between about 20 μm and about 1000 μm, between about 40 μm and about 500 μm, between about 60 μm and about 400 μm, between about 80 μm and about 200 μm, or between about 100 μm and about 160 μm. ### Claim 9 (depends on 1) The device of claim 1, wherein at least one of the first pair of conductors and the second pair of conductors has a trace widths ranging between about 5 μm and about 200 μm, between about 20 μm and about 100 μm, between about 40 μm and about 80 μm, between about 50 μm and about 70 μm, and between about 55 μm and about 65 μm. ### Claim 10 (depends on 1) The device of claim 1, wherein the spacing between the first ground plane and the second ground plane ranges between about 20 μm and about 1000 μm, between about 40 μm and about 500 μm, between about 60 μm and about 400 μm, between about 80 μm and about 200 μm, or between about 100 μm and about 160 μm. ### Claim 11 (depends on 1) The device of claim 1, wherein the substrate comprises at least one of ceramic, HiTCE ceramic, high-temperature ceramic, high-temperature ETC ceramic, resin, glass, an electrically insulative material, and a dielectric material. ### Claim 12 (depends on 1) The device of claim 1, wherein the integrated circuit package is a HiTCE package. ### Claim 13 (depends on 1) The device of claim 1, wherein the integrated circuit package is configured for use in high-speed communications equipment. ### Claim 14 (depends on 1) The device of claim 1, wherein the first and second pairs of differential signal conductors are formed from at least one of copper, a metal, a metal alloy, aluminum, gold, and silver. ### Claim 15 (depends on 1) The device of claim 1, wherein a spacing between the first and second pairs of conductors increases along at least portions of the first plane. ### Claim 16 (depends on 1) The device of claim 1, wherein the first or second ground trace has a width that increases as the spacing between the first and second pairs of conductors increases. ### Claim 17 (depends on 1) The device of claim 1, wherein the first ground plane is electrically connected to the first ground trace or the second ground plane is electrically connected to the second ground trace along about every 0.35 mm of ground trace length, about every 0.5 mm of ground trace length, about every 0.84 mm of ground trace length, about every 1 mm of ground trace length, about every 3 mm of trace length, about every 4 mm of ground trace length, about every 5 mm of ground trace length, about every 6 mm of trace length, about every 8 mm of ground trace length, or about every 10 mm of trace length. ### Claim 18 (depends on 1) The device of claim 1, wherein the impedance of the first and second differential signal conductor pairs ranges between about 50 ohms and about 150 ohms, or about 75 ohms and about 125 ohms. ### Claim 19 A method of making an integrated circuit package configured to reduce cross-talk and maintain constant impedance in first and second differential signal conductor pairs incorporated therein, comprising providing a substrate, providing first and second ground planes disposed above and below the substrate, respectively, providing respective first and second pairs of first and second differential signal conductors disposed within the substrate and substantially in a first plane, providing a third pair of victim conductors disposed within the substrate and substantially in the first plane, the third pair of victim conductors further being disposed between the first and second differential signal conductor pairs; and providing first and second ground traces disposed, respectively, between the first pair of differential signal conductors and the third pair of victim conductors, and between the second pair of differential signal conductors and the third pair of victim conductors, wherein the first and second ground traces are electrically connected to the first and second ground planes, and further wherein the widths of the first and second ground traces are varied along their respective routes within the substrate to maintain constant impedance in the first and second pairs of differential signal conductors. ### Claim 20 (depends on 19) The method of claim 19, further comprising maintaining a constant spacing between the first and second pairs of differential signal conductors. ### Claim 21 (depends on 19) The method of claim 19, further comprising changing a spacing between the first and second pairs of differential signal conductors. ### Claim 22 (depends on 21) The method of claim 21, wherein the spacing changes are configured to accommodate pitch differences. ### Claim 23 (depends on 22) The method of claim 22, wherein the pitch differences are associated with changes occurring between the integrated circuit package and a printed circuit board. ### Claim 24 (depends on 19) The method of claim 19, wherein the substrate comprises at least one of ceramic, high-temperature ceramic, high-temperature ETC ceramic, resin, glass, an electrically insulative material, and a dielectric material. ### Claim 25 (depends on 19) The method of claim 19, wherein the integrated circuit package is a HiTCE package. ### Claim 26 (depends on 19) The method of claim 19, wherein the integrated circuit package is configured for use in high-speed communications equipment. ### Claim 27 (depends on 19) The method of claim 19, wherein a spacing between the first and second pairs of conductors increases along at least portions of the first plane. ### Claim 28 (depends on 27) The method of claim 27, wherein the first or second ground trace has a width that increases as the spacing between the first and second pairs of conductors increases.