# US 7,609,117 B2 · Phase-locked loop circuit with current-pulse injection for improving linearity > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,609,117 B2 - Document ID: US7609117B2 - Status: Granted - Kind: B2 - Application number: 10/801,482 - Filed: 2004-03-15 - Published: 2004-10-21 - Granted: 2009-10-27 - Earliest claimed: 2003-03-14 - Assignees: STMicroelctronics S.r.l. - Inventors: Enrico Temporiti Milani; Guido Gabriele Albasini - Web page: https://patentgrep.com/patent/US7609117B2 ## CPC - H03L 7/1974: {for fractional frequency division} - H03L 7/0891: {the up-down pulses controlling source and sink current generators, e.g. a charge pump} - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract A phase-locked loop circuit is proposed for providing an output signal having a frequency depending on the frequency of a reference signal, the circuit including means for deriving a feedback signal from the output signal, means for providing a control signal indicative of a phase difference between the reference signal and the feedback signal, means for controlling the frequency of the output signal according to the control signal, and means for causing the circuit to enter a lock condition when the reference signal and the feedback signal have the same frequency and a pre-defined phase difference. In the circuit of an embodiment of the invention, the means for causing the circuit to enter the lock condition includes means for conditioning the control signal to have an instantaneous value substantially zero in the lock condition by means of a conditioning signal consisting of a series of pulses each one corresponding to the pre-defined phase difference. ## Claims ### Claim 1 A phase-locked loop circuit for providing an output signal having a frequency depending on the frequency of a reference signal, the circuit including means for deriving a feedback signal from the output signal, means for providing a control signal indicative of a phase difference between the reference signal and the feedback signal, means for controlling the frequency of the output signal according to the control signal, and means for causing the circuit to enter a lock condition when the reference signal and the feedback signal have the same frequency and a pre-defined phase difference, the means for causing the circuit to enter the lock condition including means for conditioning the control signal to have an instantaneous value of substantially zero in the lock condition by means of a conditioning signal consisting of a series of pulses each one corresponding to the pre-defined phase difference. ### Claim 2 (depends on 1) The circuit according to claim 1, wherein the means for providing the control signal includes means for generating a phase indicator signal consisting of a series of pulses each one indicative of a phase difference between the reference signal and the feedback signal, and wherein the means for conditioning includes means for adding the conditioning signal to the phase indicator signal, the pulses of the phase indicator signal being opposite to the pulses of the conditioning signal in the lock condition. ### Claim 3 (depends on 2) The circuit according to claim 2, wherein the means for generating the phase indicator signal includes means for setting a first indicator signal in response to a switching edge of the reference signal, means for setting a second indicator signal in response to the switching edge of the feedback signal, means for resetting the first indicator signal and the second indicator signal in response to the setting of both the first and the second indicator signals, and means for combining the first indicator signal and the second indicator signal into the phase indicator signal, the switching edges of the reference signal and of the feedback signal being synchronous with the pulses of the conditioning signal in the lock condition. ### Claim 4 (depends on 1) The circuit according to claim 1, wherein the means for conditioning includes means for generating the pulses of the conditioning signal synchronously with a selected one between the reference signal and the feedback signal. ### Claim 5 (depends on 4) The circuit according to claim 4, wherein the selected signal consists of the feedback signal, the means for generating the conditioning signal including means for deriving the conditioning signal from the output signal. ### Claim 6 (depends on 5) The circuit according to claim 5, wherein the means for deriving the conditioning signal from the output signal includes means for generating the switching edge and a further switching edge of each pulse of the conditioning signal in response to a first switching edge and to a second switching edge, respectively, of the output signal, the second switching edge of the output signal corresponding to the switching edge of the feedback signal and the first switching edge of the output signal preceding the second switching edge of the output signal by a pre-defined number of periods of the output signal. ### Claim 7 (depends on 6) The circuit according to claim 6, wherein the means for generating the feedback signal includes a multi-modulus divider (for deriving a pre-scaled signal from the output signal, the means for deriving the conditioning signal from the output signal being clocked by the pre-scaled signal. ### Claim 8 (depends on 1) The circuit according to claim 1, wherein the phase-locked loop circuit is of a fractional type. ### Claim 9 In a phase-locked loop circuit, a method of providing an output signal having a frequency depending on the frequency of a reference signal, the method including the steps of: deriving a feedback signal from the output signal, providing a control signal indicative of a phase difference between the reference signal and the feedback signal, controlling the frequency of the output signal according to the control signal, and causing the circuit to enter a lock condition when the reference signal and the feedback signal have the same frequency and a pre-defined phase difference, wherein causing the circuit to enter the lock condition includes: conditioning the control signal to have an instantaneous value substantially zero in the lock condition by means of a conditioning signal consisting of a series of pulses each one corresponding to the pre-defined phase difference. ### Claim 10 A phase-locked loop for producing an output signal, the phase-locked loop comprising: a first circuit operable to produce a first signal that represents a phase difference between a feedback signal and a reference signal; and a second circuit coupled to the first circuit, the second circuit operable to produce a second signal, the second signal being controlled to vary over time, and to combine the second signal with the first signal to produce a control signal having an instantaneous value substantially equal to zero. ### Claim 11 (depends on 10) The loop of claim 10 wherein the control signal having the instantaneous value substantially equal to zero indicates a locked condition of the loop. ### Claim 12 A phase-locked loop for producing an output signal, comprising: a first circuit operable to produce a first signal characterizing a phase difference between a feedback signal and a reference signal; and a second circuit coupled to the first circuit, the second circuit operable to produce a second signal having a rising edge corresponding to a rising edge of the feedback signal, the second circuit further operable to couple the second signal to the first signal to produce a control signal having an instantaneous value substantially equal to zero. ### Claim 13 A phase-locked loop for producing an output signal, comprising: a first circuit operable to produce a first signal characterizing a phase difference between a feedback signal and a reference signal; and a second circuit coupled to the first circuit, the second circuit operable to produce a second signal having a falling edge corresponding to a rising edge of the feedback signal, the second circuit further operable to couple the second signal to the first signal to produce a control signal having an instantaneous value substantially equal to zero. ### Claim 14 (depends on 10) The loop of claim 10 wherein the second circuit comprises a current source. ### Claim 15 A phase-locked loop for producing an output signal, comprising: a first circuit operable to produce a first signal characterizing a phase difference between a feedback signal and a reference signal; and a second circuit coupled to the first circuit, the second circuit operable to produce a second signal, the second circuit further operable to couple the second signal to the first signal to produce a control signal having an instantaneous value substantially equal to zero, the second circuit further comprising a current source and a switch operable to transition between conducting and non-conducting states, the switch further operable to couple the current source to ground when in the conducting state. ### Claim 16 (depends on 15) The loop of claim 15 wherein the second circuit further comprises a third circuit operable to produce a third signal, the third signal operable to control the switch transitions. ### Claim 17 (depends on 16) The loop of claim 16 wherein the third circuit produces the third signal from the output signal. ### Claim 18 (depends on 16) The loop of claim 16, further comprising a fourth circuit operable to produce a fourth signal from the output signal, wherein the fourth signal clocks the third circuit. ### Claim 19 A method, comprising: producing a first signal indicating a phase difference between a feedback signal and a reference signal; producing a second signal that is controlled to vary over time; and producing a control signal having an instantaneous value substantially equal to zero by combining the first and second signals. ### Claim 20 An electronic system, comprising: a phase-locked loop for producing an output signal, the phase-locked loop comprising: a first circuit operable to produce a first signal that represents a phase difference between a feedback signal and a reference signal; and a second circuit coupled to the first circuit, the second circuit operable to produce a second signal, the second signal being controlled to vary over time, and to combine the second signal with the first signal to produce a control signal having an instantaneous value substantially equal to zero. ### Claim 21 (depends on 10) The loop of claim 10 wherein combining the second signal with the first signal comprises summing the first and second signals. ### Claim 22 (depends on 19) The method of claim 19 wherein combining the first and second signals comprises summing the first and second signals. ### Claim 23 (depends on 20) The electronic system of claim 20 wherein the second circuit is operable to produce a series of pulses for the second signal. ### Claim 24 (depends on 19) The method of claim 19 wherein the second signal comprises a series of pulses. ### Claim 25 (depends on 10) The phase-locked loop of claim 10 wherein the second circuit is operable to produce a series of pulses for the second signal.