# US 7,609,115 B2 · Input circuitry for transistor power amplifier and method for designing such circuitry > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,609,115 B2 - Document ID: US7609115B2 - Status: Granted - Kind: B2 - Application number: 11/851,425 - Filed: 2007-09-07 - Published: 2009-03-12 - Granted: 2009-10-27 - Earliest claimed: 2007-09-07 - Assignees: Raytheon Company - Inventors: Colin S. Whelan; John C. Tremblay - Web page: https://patentgrep.com/patent/US7609115B2 ## CPC - H03F 1/565: {using inductive elements} - H03F 3/1935: {with junction-FET devices} - H03H 7/38: Impedance-matching networks - H03F 2200/222: A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier - H03F 2200/228: A measuring circuit being coupled to the input of an amplifier - H03F 2200/249: A switch coupled in the input circuit of an amplifier being controlled by a circuit, e.g. feedback circuitry being controlling the switch - H03F 2200/252: Multiple switches coupled in the input circuit of an amplifier are controlled by a circuit, e.g. feedback circuitry being controlling the switch - H03F 2200/451: the amplifier being a radio frequency amplifier - H03F 2200/99: A diode as rectifier being used as a detecting circuit in an amplifying circuit - H03F: AMPLIFIERS - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) ## Abstract A circuit having: an input matching network; a transistor coupled to an output of the input matching network; and wherein the input matching network has a first input impedance when such input matching network is fed with an input signal having a relatively low power level and wherein the input matching network has an input impedance different from the first input impedance when such input matching network is fed with an input signal having a relatively high power level. ## Claims ### Claim 1 A circuit, comprising: an input impedance matching network; a transistor coupled to an output of the impedance matching network; and wherein the input matching network has a first input impedance when such input matching network is fed with an input signal having a relatively low power level and wherein the input matching network has an input impedance different from the first input impedance when such input matching network is fed with an input signal having a relatively high power level. ### Claim 2 (depends on 1) The circuit recited in claim 1 wherein the transistor has a field plate. ### Claim 3 (depends on 1) The circuit recited in claim 1 wherein the transistor is a gallium nitride transistor. ### Claim 4 (depends on 3) The circuit recited in claim 3 wherein the transistor has a field plate. ### Claim 5 A circuit, comprising; a transistor having an input electrode; an input matching network having an input fed by an input signal and having an output connected to the input electrode of the transistors; a power level sensing circuit fed by the input signal; and wherein the input matching network is responsive to the power level sensing circuit to: configure the input matching network with a first input impedance when such power level sensing circuit senses the input signal has a relatively low power level; and configure the input matching network with an input impedance different from the first input impedance when such power level sensing circuit senses the input signal has a relatively high power level. ### Claim 6 (depends on 5) The circuit recited in claim 5 wherein the transistor has a field plate. ### Claim 7 (depends on 5) The circuit recited in claim 5 wherein the transistor is a gallium nitride transistor. ### Claim 8 (depends on 7) The circuit recited in claim 7 wherein the transistor has a field plate. ### Claim 9 A circuit, comprising; a transistor having an input electrode; an input matching network having an input fed by an input signal and having an output connected to the input electrode of the transistors; a power level sensing circuit fed by the input signal; wherein the input matching network is responsive to the power level sensing circuit to: configure the input matching network with a first input impedance when such power level sensing circuit senses the input signal has a relatively low power level; and configure the input matching network with an input impedance different from the first input impedance when such power level sensing circuit senses the input signal has a relatively high power level; and wherein the input matching network has a first inductor serially coupled between the input signal and the input electrode of the transistor when such power level sensing circuit senses the input signal has the relatively high power level and wherein the input matching network has a second inductor serially coupled between the input signal and the input electrode of the transistor when such power level sensing circuit senses the input signal has the relatively low power level. ### Claim 10 (depends on 9) The circuit recited in claim 9 wherein the transistor has a field plate. ### Claim 11 (depends on 9) The circuit recited in claim 9 wherein the transistor is a gallium nitride transistor. ### Claim 12 (depends on 11) The circuit recited in claim 11 wherein the transistor has a field plate. ### Claim 13 (depends on 9) The circuit recited in claim 9 wherein the transistor is a field effect transistor and wherein the input electrode is a gate electrode of such transistor. ### Claim 14 (depends on 13) The circuit recited in claim 13 wherein the transistor has a field plate. ### Claim 15 (depends on 13) The circuit recited in claim 13 wherein the transistor is a gallium nitride transistor. ### Claim 16 (depends on 15) The circuit recited in claim 15 wherein the transistor has a field plate. ### Claim 17 A circuit, comprising; a transistor having an input electrode; an input matching network having an input fed by an input signal and having an output connected to the input electrode of the transistors; a power level sensing circuit fed by the input signal; and wherein the input matching network is responsive to the power level sensing circuit to: configure the input matching network with a first input impedance when such power level sensing circuit senses the input signal has a relatively low power level; and configure the input matching network with an input impedance different from the first input impedance when such power level sensing circuit senses the input signal has a relatively high power level; wherein the input matching network includes: a pair of electrical components; and at least one switch, and wherein the at least one switch operates in response to the power level sensing circuit to electrically decouple one of the pair of electrical components from the input matching network at one of the relatively high or relatively low power levels and operates to electrically couple said one of the pair of electrical components to the input matching network at the other one of the relatively high or relatively low power levels. ### Claim 18 (depends on 17) The circuit recited in claim 17 wherein the electrical components are inductors having different inductances. ### Claim 19 (depends on 1) The circuit recited in claim 1 wherein the input matching network includes: a pair of reactive electrical components; and at least one switch, and wherein the at least one switch operates in response to the power level sensing circuit to electrically decouple one of the pair of reactive electrical components from the input matching network at one of the relatively high or relatively low power levels and operates to electrically couple said one of the pair of reactive electrical components to the input matching network at the other one of the relatively high or relatively low power levels.