# US 7,609,103 B2 · Delay circuit with reference pulse generator to reduce variation in delay time > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,609,103 B2 - Document ID: US7609103B2 - Status: Granted - Kind: B2 - Application number: 12/132,870 - Filed: 2008-06-04 - Published: 2008-12-11 - Granted: 2009-10-27 - Earliest claimed: 2007-06-05 - Assignees: NEC Electronics Corporation - Inventors: Toshiaki Motoyui - Web page: https://patentgrep.com/patent/US7609103B2 ## CPC - H03K 5/1515: {non-overlapping} - H03K 5/04: by increasing duration; by decreasing duration - H03K 19/0016: {by using a control or a clock signal, e.g. in order to apply power supply} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A delay circuit to generate and output a delayed signal delayed from an input signal includes a reference pulse generating circuit to generate a reference pulse train in response to the input of the input signal, the reference pulse generating circuit having a feedback circuit containing a delay portion to determine a time interval between the reference pulses, a counter to output count signals based on a reference clock, the counter receiving the reference pulse train generated by the reference pulse generating circuit as the reference clock, and a delayed signal output circuit to generate and output the delayed signal based on the input signal and the count signals. ## Claims ### Claim 1 A delay circuit to generate and output a delayed signal delayed from an input signal comprising: a reference pulse generating circuit to generate a reference pulse train in response to the input of the input signal, the reference pulse generating circuit having a feedback circuit containing a delay portion to determine a time interval between the reference pulses; a counter to output count signals based on a reference clock, the counter receiving the reference pulse train generated by the reference pulse generating circuit as the reference clock; and a delayed signal output circuit to generate and output the delayed signal based on the input signal and the count signals. ### Claim 2 (depends on 1) The delay circuit according to claim 1, wherein the delay portion determines the time interval between the reference pulses based on the delay amount in the signal outputted by the delay portion from the signal inputted to the delay portion. ### Claim 3 (depends on 1) The delay circuit according to claim 1, wherein the delay portion generates a delay pulse train used to generate the reference pulse train; and the feedback circuit further includes a calculation circuit to output the logical product of a signal generated based on the delayed signal and the delay pulse train, and the input signal to the delay portion. ### Claim 4 (depends on 2) The delay circuit according to claim 2, wherein the delay portion generates a delay pulse train used to generate the reference pulse train; and the feedback circuit further includes a calculation circuit to output the logical product a signal generated based on the delayed signal and the delay pulse train, and the input signal to the delay portion. ### Claim 5 (depends on 3) The delay circuit according to claim 3, wherein the delay portion causes the calculation circuit to generate an input pulse train having the time interval by feeding back the delayed pulse delayed from the signal inputted from the calculation circuit by the time interval to the calculation circuit, and outputs the delayed pulse train delayed from the input pulse train. ### Claim 6 (depends on 1) The delay circuit according to claim 1, wherein the counter has a plurality of flip-flop circuits to generate the count signals, each of the count signals being composed of a first logical value and a second logical value different from the first logical value; and the plurality of flip-flop circuits outputs the count signals to the delayed signal output circuit, the count signals being changed from the first logical value to the second logical value with different timings from each other upon the input of the reference pulse train. ### Claim 7 (depends on 2) The delay circuit according to claim 2, wherein the counter has a plurality of flip-flop circuits to generate the count signals, each of the count signals being composed of a first logical value and a second logical value different from the first logical value; and the plurality of flip-flop circuits outputs the count signals to the delayed signal output circuit, the count signals being changed from the first logical value to the second logical value with different timings from each other upon the input of the reference pulse train. ### Claim 8 (depends on 3) The delay circuit according to claim 3, wherein the counter has a plurality of flip-flop circuits to generate the count signals, each of the count signals being composed of a first logical value and a second logical value different from the first logical value; and the plurality of flip-flop circuits outputs the count signals to the delayed signal output circuit, the count signals being changed from the first logical value to the second logical value with different timings from each other upon the input of the reference pulse train. ### Claim 9 (depends on 4) The delay circuit according to claim 4, wherein the counter has a plurality of flip-flop circuits to generate the count signals, each of the count signals being composed of a first logical value and a second logical value different from the first logical value; and the plurality of flip-flop circuits outputs the count signals to the delayed signal output circuit, the count signals being changed from the first logical value to the second logical value with different timings from each other upon the input of the reference pulse train. ### Claim 10 (depends on 1) The delay circuit according to claim 1, wherein the delayed signal output circuit generates the delayed signal based on the logical product of the input signal and the count signals. ### Claim 11 (depends on 2) The delay circuit according to claim 2, wherein the delayed signal output circuit generates the delayed signal based on the logical product of the input signal and the count signals. ### Claim 12 (depends on 3) The delay circuit according to claim 3, wherein the delayed signal output circuit generates the delayed signal based on the logical product of the input signal and the count signals. ### Claim 13 (depends on 1) The delay circuit according to claim 1, further comprising a reset signal output circuit to generate a reset signal based on the delayed signal, and output the generated reset signal to the counter. ### Claim 14 (depends on 2) The delay circuit according to claim 2, further comprising a reset signal output circuit to generate a reset signal based on the delayed signal, and output the generated reset signal to the counter. ### Claim 15 (depends on 3) The delay circuit according to claim 3, further comprising a reset signal output circuit to generate a reset signal based on the delayed signal, and output the generated reset signal to the counter. ### Claim 16 (depends on 4) The delay circuit according to claim 4, further comprising a reset signal output circuit to generate a reset signal based on the delayed signal, and output the generated reset signal to the counter. ### Claim 17 (depends on 1) The delay circuit according to claim 1, further comprising a selector to select one count signal from the plurality of count signals outputted from the counter, and output the selected count signal to the delayed signal output circuit based on a select signal. ### Claim 18 (depends on 2) The delay circuit according to claim 2, further comprising a selector to select one count signal from the plurality of count signals outputted from the counter, and output the selected count signal to the delayed signal output circuit based on a select signal. ### Claim 19 (depends on 3) The delay circuit according to claim 3, further comprising a selector to select one count signal from the plurality of count signals outputted from the counter, and output the selected count signal to the delayed signal output circuit based on a select signal. ### Claim 20 (depends on 4) The delay circuit according to claim 4, further comprising a selector to select one count signal from the plurality of count signals outputted from the counter, and output the selected count signal to the delayed signal output circuit based on a select signal.