# US 7,609,100 B2 · On-chip signal waveform measurement apparatus for measuring signal waveforms at detection points on IC chip

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,609,100 B2
- Document ID: US7609100B2
- Status: Granted
- Kind: B2
- Application number: 11/826,271
- Filed: 2007-07-13
- Published: 2007-11-15
- Granted: 2009-10-27
- Earliest claimed: 2005-03-03
- Assignees: Semiconductor Technology Academic Research Center
- Inventors: Makoto Nagata
- Web page: https://patentgrep.com/patent/US7609100B2

## CPC

- G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)}
- G01R 31/31924: {Voltage or current aspects, e.g. driver, receiver}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

An on-chip signal waveform measurement apparatus mounted on an IC chip measures signal waveforms at detection points on the IC chip. A reference voltage generator successively generates reference voltages different from each other based on a predetermined timing signal, and Signal probing front-end circuits are mounted to correspond to the detection points, respectively, and each buffer-amplifies a voltage at each detection point, compares the buffer-amplified voltage with each reference voltage, and digitizes a comparison result into a binary digital output signal. A multiplexer time-division-multiplexes the binary digital output signals from the signal probing front-end circuits. A data processing unit calculates a judgment output probability for a detected voltage at each detection point detected by the respective signal probing front-end circuits, by counting a number of times of a predetermined binary value of the multiplexed binary digital output signal.

## Claims

### Claim 1

A sampling timing signal generator for generating an enable timing control signal based on a predetermined system clock signal and a predetermined master clock signal, said sampling timing signal generator comprising:
a replica DLL (Delayed Locked Loop) circuit configured to generate a predetermined reference bias voltage in synchronization with the system clock signal based on the system clock signal, and to output the reference bias voltage; and
a delay signal generator circuit configured to operate for integers n (where “n” is an integer equal to or larger than one) and to generate a current obtained by dividing a reference current corresponding to the reference bias voltage by “n”, to use the generated divided current for charging an output load capacitance whereby the time for charging the output load capacitance constitutes a desired time delay, the desired time delay being a multiplication product of the number n and an arbitrary delay time to delay the master clock signal by the desired delay time, and to generate a delayed signal as an enable timing control signal,
wherein said replica DLL circuit is configured to generate the reference bias voltage so that the desired delay time is equal to a cycle of the system clock signal, whereby said delay signal generator circuit generates the enable timing control signal.