# US 7,609,099 B2 · Power-on detecting circuit

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- Number: US 7,609,099 B2
- Document ID: US7609099B2
- Status: Granted
- Kind: B2
- Application number: 11/558,156
- Filed: 2006-11-09
- Published: 2007-05-24
- Granted: 2009-10-27
- Earliest claimed: 2005-11-18
- Assignees: Kabushiki Kaisha Toshiba
- Inventors: Ryu Ogiwara; Daisaburo Takashima
- Web page: https://patentgrep.com/patent/US7609099B2

## CPC

- G01R 19/16552: {in I.C. power supplies}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A circuit for detecting a power-on voltage of power supply encompasses a voltage divider connected between a first power supply and a second power supply, the potential of the second power supply is lower than the potential of the first power supply, and a detecting circuit connected between the first power supply and the second power supply. The voltage divider includes a series circuit encompassing a diode, a first dividing resistor connected to the diode and a second dividing resistor connected between the first dividing resistor and the second power supply. The detecting circuit includes a pMOS transistor whose gate electrode is connected to a connection node between the first dividing resistor and the second dividing resistor, a source resistor connected between the first power supply and the source electrode of the pMOS transistor and a drain resistor connected to the drain electrode of the pMOS transistor and the second power supply.

## Claims

### Claim 1

A circuit for detecting a power-on voltage of a power supply, comprising:
a voltage divider connected between a first power supply and a second power supply, the potential of the second power supply is lower than the potential of the first power supply, the voltage divider including a series circuit which includes:
a diode;
a first dividing resistor connected to the diode; and
a second dividing resistor connected between the first dividing resistor and the second power supply; and
a detecting circuit connected between the first power supply and the second power supply, the detecting circuit including:
a pMOS transistor whose gate electrode is connected to a connection node between the first dividing resistor and the second dividing resistor;
a source resistor connected between the first power supply and the source electrode of the pMOS transistor; and
a drain resistor connected to the drain electrode of the pMOS transistor and the second power supply,
wherein a resistance value R1 of the first dividing resistor, a resistance value R2 of the second dividing resistor, a resistance value R3 of the source resistor R3 and a resistance value R4 of the drain resistor satisfy:
R2/(R1+R2)=(dVth/dT×R4/(R3+R4))/(dVdio/dT),
where dVth/dT is a temperature dependence of a threshold voltage of the pMOS transistor, and dVdio/dT is a temperature dependence of an on-state voltage of the diode.

### Claim 2 (depends on 1)

The circuit of claim 1, further comprising a divider series resistor connected between the first power supply and the diode.

### Claim 3 (depends on 2)

The circuit of claim 2, further comprising a second source resistor connected between the first power supply and the source resistor.

### Claim 4 (depends on 1)

The circuit of claim 1, further comprising a divider series resistor connected between the diode and the first dividing resistor.

### Claim 5 (depends on 4)

The circuit of claim 4, further comprising a second source resistor connected between the first power supply and the source resistor.

### Claim 6

A circuit for detecting a power-on voltage of a power supply, comprising:
a voltage divider connected between a first power supply and a second power supply, the potential of the second power supply is lower than the potential of the first power supply, the voltage divider including a series circuit which includes:
a diode-connected first pMOS transistor;
a first dividing resistor connected to the first pMOS transistor; and
a second dividing resistor connected between the first dividing resistor and the second power supply; and
a detecting circuit connected between the first power supply and the second power supply, the detecting circuit including:
a second pMOS transistor whose gate electrode is connected to a connection node between the first dividing resistor and the second dividing resistor; and
a drain resistor connected to the drain electrode of the second pMOS transistor and the second power supply,
wherein a resistance value R1 of the first dividing resistor and a resistance value R2 of the second dividing resistor satisfy:
|dVGS1/dT|×R2/(R1+R2)=|dVGS2/dT|
where dVGS1/dT is a temperature dependence of gate-source voltage of the first pMOS transistor, and dVGS2/dT is a temperature dependence of gate-source voltage of the second pMOS transistor.

### Claim 7 (depends on 6)

The circuit of claim 6, further comprising a divider series resistor connected between the first power supply and the first pMOS transistor.

### Claim 8 (depends on 7)

The circuit of claim 7, further comprising a source resistor connected between the first power supply and the source electrode of the second pMOS transistor.

### Claim 9 (depends on 6)

The circuit of claim 6, further comprising a divider series resistor connected between the first pMOS transistor and the first dividing resistor.

### Claim 10 (depends on 9)

The circuit of claim 9, further comprising a source resistor connected between the first power supply and the source electrode of the second pMOS transistor.

### Claim 11

A circuit for detecting a power-on voltage of power supply, comprising:
a voltage divider connected between a first power supply and a second power supply, the potential of the second power supply is lower than the potential of the first power supply, the voltage divider including a series circuit comprising:
a diode-connected first divider pMOS transistor;
a diode-connected second divider pMOS transistor connected to the first divider pMOS transistor;
a first dividing resistor connected to the second divider pMOS transistor; and
a second dividing resistor connected between the first dividing resistor and the second power supply; and
a detecting circuit connected between the first power supply and the second power supply, the detecting circuit including:
a detecting pMOS transistor whose gate electrode is connected to a connection node between the first dividing resistor and the second dividing resistor;
a source resistor connected between the first power supply and the source electrode of the detecting pMOS transistor; and
a drain resistor connected to the drain electrode of the detecting pMOS transistor and the second power supply
wherein, with gate width W and gate length L, ratios W/L in the first and second divider pMOS transistors are equal,
wherein resistance values of the first and second dividing resistors are equal.

### Claim 12

A circuit for detecting a power-on voltage of a power supply, comprising:
a voltage divider connected between a first power supply and a second power supply, the potential of the second power supply is lower than the potential of the first power supply, the voltage divider including a series circuit comprising:
a diode-connected first divider pMOS transistor;
a diode-connected second divider pMOS transistor connected to the first divider pMOS transistor;
a first dividing resistor connected to the second divider pMOS transistor; and
a second dividing resistor connected between the first dividing resistor and the second power supply; and
a detecting circuit connected between the first power supply and the second power supply, the detecting circuit including:
a detecting pMOS transistor whose gate electrode is connected to a connection node between the first dividing resistor and the second dividing resistor;
a source resistor connected between the first power supply and the source electrode of the detecting pMOS transistor; and
a drain resistor connected to the drain electrode of the detecting pMOS transistor and the second power supply,
wherein a relationship given by:
Vdd−{Vdd−|VGS1|−|VGS2|}/2=|VGS3|
is satisfied, where Vdd is a potential supplied by the first power supply, VGS1 is a gate-source voltage of the first divider pMOS transistor, VGS2 is a gate-source voltage of the second divider pMOS transistor and VGS3 is a gate-source voltage of the detecting pMOS transistor.