# US 7,609,096 B1 · Frequency synthesizer and method for constructing the same

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- Number: US 7,609,096 B1
- Document ID: US7609096B1
- Status: Granted
- Kind: B1
- Application number: 12/138,936
- Filed: 2008-06-13
- Granted: 2009-10-27
- Earliest claimed: 2008-06-13
- Inventors: Edward C. Chang; Deirdre McGlashan; Meimei Chang
- Web page: https://patentgrep.com/patent/US7609096B1

## CPC

- H03B 21/00: Generation of oscillations by combining unmodulated signals of different frequencies (H03B19/00 takes precedence; frequency changing circuits in general H03D)
- G06F 1/022: {Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers (G06F1/025, G06F1/03 take precedence)}
- H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00)
- H03L 7/091: the phase or frequency detector using a sampling device (H03L7/087 takes precedence)
- H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence)
- H03L 7/107: using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03B: GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS (generators adapted for electrophonic musical instruments G10H; masers or lasers H01S; generation of oscillations in plasma H05H)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A frequency synthesizer and a method for constructing the same by using the architecture of digital process frequency loop (DPFL) are disclosed. The DPFL frequency synthesizer with the DPFL architecture includes a reference frequency divider counter, an output divider counter, a processor, a memory, a digital to analog converter (DAC), and a voltage Control Oscillator (VCO). The method uses the processor to perform the signal processing to correct the output frequency of the VCO in the frequency domain. The memory stores the nonlinear characteristics of the VCO such that the synthesizer is completely controlled, no uncertain frequency being captured during process, and the frequency resolution of the synthesizer is programmable.

## Claims

### Claim 1

A frequency synthesizer having a reference frequency as an input signal and an output frequency as an output signal, the frequency synthesizer comprising:
an N1 counter for dividing said reference frequency by a number of N1, and delivering an enable signal;
an N2 counter for receiving said enable signal, dividing said output frequency by a number of N2 when said enable signal is active, and delivering a digital output data;
a processor for receiving said output data of said N2 counter and delivering a digital output data;
a digital to analog converter (DAC) for receiving and converting said output data of said processor and delivering an analog output signal; and
a voltage control oscillator (VCO) for receiving said output signal of said DAC and delivering said output frequency;
wherein said DAC comprises a DAC register for storing said output data of said processor for said DAC to generate said output signal.

### Claim 2 (depends on 1)

The frequency synthesizer as claimed in claim 1, wherein said enable signal is active for said N2 counter when said enable signal is a high logic level, and said enable signal is inactive for said N2 counter when said enable signal is a low logic level.

### Claim 3 (depends on 1)

The frequency synthesizer as claimed in claim 1, wherein said enable signal is active for said N2 counter when said enable signal is a low logic level, and said enable signal is inactive for said N2 counter when said enable signal is a high logic level.

### Claim 4 (depends on 1)

The frequency synthesizer as claimed in claim 1, wherein said processor comprises:
a programmed holding register for storing a target frequency programmed by an external control device and delivering an output data;
a DAC holding register for receiving said output data of said programmed holding register, and delivering an output data coupled to said output data of said processor;
a first arithmetic logic unit (ALU) for subtracting said output data of said N2 counter from said output data of said programmed holding register, and delivering an output data; and
a second ALU for adding said output data of said DAC holding register to said output data of said first ALU, and delivering an output data coupled to said DAC holding register;
wherein said DAC holding register further comprises an input Hold/Update port to set said DAC holding register in a Hold or Update mode; and said output data of said DAC holding register is not changed in said Hold mode.

### Claim 5 (depends on 1)

The frequency synthesizer as claimed in claim 1, wherein said N1 counter is a fixed counter.

### Claim 6 (depends on 1)

The frequency synthesizer as claimed in claim 1, wherein said N1 counter is a programmable counter.

### Claim 7

A frequency synthesizer having a reference frequency as an input signal and an output frequency as an output signal, the frequency synthesizer comprising:
an N1 counter for dividing said reference frequency by a number of N1 and delivering an enable signal;
an N2 counter for receiving said enable signal from said N1 counter, dividing said output frequency by a number of N2 when said enable signal is active, and delivering an output data;
a processor for receiving said output data of said N2 counter and delivering an output data;
a memory for receiving said output data of said processor and delivering an output data;
a digital to analog converter (DAC) for receiving and converting said output data of said memory and delivering an analog output signal; and
a voltage control oscillator (VCO) for receiving said output signal of said DAC and delivering said output frequency;
wherein said DAC comprises a DAC register for storing said output data of said memory for said DAC to generate said output signal.

### Claim 8 (depends on 7)

The frequency synthesizer as claimed in claim 7, wherein said enable signal is active for said N2 counter when said enable signal is a high logic level, and said enable signal is inactive for said N2 counter when said enable signal is a low logic level.

### Claim 9 (depends on 7)

The frequency synthesizer as claimed in claim 7, wherein said enable signal is active for said N2 counter when said enable signal is a low logic level, and said enable signal is inactive for said N2 counter when said enable signal is a high logic level.

### Claim 10 (depends on 7)

The frequency synthesizer as claimed in claim 7, wherein said processor comprises:
a programmed holding register for storing a value of a target frequency programmed by an external control device and delivering an output data;
a DAC holding register for receiving said output data of said programmed holding register, and delivering an output data coupled to said output signal of said processor;
a first arithmetic logic unit (ALU) for subtracting said output data of said N2 counter from said output data of said programmed holding register, and delivering an output data; and
a second ALU for adding said output data of said DAC holding register to said output data of said first ALU, and delivering an output data to said DAC holding register;
wherein said DAC holding register further comprises an input Hold/Update port to set said DAC holding register in a Hold or Update mode; and said output data of said DAC holding register is not changed in said Hold mode.

### Claim 11 (depends on 7)

The frequency synthesizer as claimed in claim 7, wherein said DAC holding register is initially set in said Hold mode, said DAC register is not changed by said output data of said memory, and said external control device writes an initial value to said DAC register as said target frequency;
said DAC generates said output signal, and said VCO generates said output frequency;
said output frequency is divided and counted by said N2 counter to generate said output data as a measured frequency for said output frequency;
said measured frequency of said N2 counter is checked by said external control device if said output frequency matches said value stored in said programmed holding register as said target frequency;
said output data of said DAC holding register coupled to said memory is not changed when said output signal of said N2 counter changes because said DAC holding register is in said Hold mode;
said DAC register keeps loading a new data from said external control device and said DAC, VCO, and N2 counter perform said same operation until said output frequency matches said value stored in said programmed holding register;
said DAC register is fetched by said external control device to obtain a frequency corrected data;
said output data of said processor is coupled to said memory as a memory address of said memory, said frequency corrected data is a memory write data of said memory, and said memory is written with said memory address and said memory write data by said external control device; and
said DAC holding register is set in said Update mode after all frequency corrected data are stored in said memory, said DAC register is updated by said output data of said memory, and said output frequency generated by said VCO matches said target frequency as specified in said programmed holding register by said external control device.

### Claim 12 (depends on 7)

The frequency synthesizer as claimed in claim 7, wherein said N1 counter is a fixed counter.

### Claim 13 (depends on 7)

The frequency synthesizer as claimed in claim 7, wherein said N1 counter is a programmable counter.

### Claim 14 (depends on 7)

The frequency synthesizer as claimed in claim 7, wherein said memory and said DAC are replaced by a coarse memory, a coarse DAC, a vernier memory, a vernier DAC, and a summing amplifier;
said coarse memory receives said output signal from said processor and delivers an output signal coupled to said coarse DAC;
said vernier memory receives said output signal from said processor and delivers an output signal coupled to said vernier DAC;
said coarse DAC delivers an output signal coupled to said summation amplifier;
said vernier DAC delivers an output signal coupled to said summing amplifier;
an LSB voltage of said coarse DAC equals to a full scale of said vernier DAC minus one LSB;
said summing amplifier receives and sums up the output signals from said coarse DAC and said vernier DAC to obtain a summed signal, said summed signal is amplified, and said summing amplifier delivers an output signal coupled to said VCO.

### Claim 15 (depends on 7)

The frequency synthesizer as claimed in claim 7, wherein said memory and said DAC are replaced by a coarse memory, a coarse DAC, a vernier memory, a vernier DAC, a summing amplifier, and a modulation amplifier;
said coarse memory receives said output signal from said processor and delivers an output signal coupled to said coarse DAC;
said vernier memory receives said output signal from said processor and delivers an output signal coupled to said vernier DAC;
said coarse DAC delivers an output signal coupled to said summation amplifier;
said vernier DAC delivers an output signal coupled to said summation amplifier;
an LSB voltage of said coarse DAC equals to a full scale of said vernier DAC minus one LSB;
said summing amplifier receives and sums up the output signals from said coarse DAC and said vernier DAC to obtain a summed signal, and said summed signal is amplified and said summing amplifier delivers an output signal coupled to said modulation amplifier;
said modulation amplifier sums up and amplifies said output signal of said summation amplifier and a modulation information signal to generate an output signal coupled to said VCO;
said DAC holding register is set to said Hold mode after said VCO is settled and before said output frequency drifts off to keep said summed signal, and said output frequency of said VCO modulated by said modulation information signal.

### Claim 16 (depends on 15)

The frequency synthesizer as claimed in claim 15, wherein said programmed holding register is loaded with a carrier frequency of a modulated frequency modulation (FM) signal from an external signal source, said N2 counter receives and measures said modulated FM signal to deliver a modulated frequency, said first ALU subtracts said carrier frequency in said programmed holding register from said modulated frequency to deliver a demodulated signal.

### Claim 17

A method for constructing a frequency synthesizer having an N1 counter, an N2 counter, a processor, a DAC, and a VCO, the method comprising the steps of:
inputting a reference frequency to said N1 counter as a time base for said frequency synthesizer;
driving said N1 counter to generate an enable signal by dividing said reference frequency by a number of N1;
driving said N2 counter to generate an output data coupled to said processor by dividing an output frequency of said VCO by a number of N2 when said enable signal is active;
driving said processor to generate an output data coupled to a DAC register of said DAC;
driving said DAC to generate an analog output signal coupled to a VCO by said output data of said DAC register; and
driving said VCO to generate said output frequency coupled to said N2 counter.

### Claim 18 (depends on 17)

The method as claimed in claim 17, wherein said enable signal is active for said N2 counter when said enable signal is a high logic level, and said enable signal is inactive for said N2 counter when said enable signal is a low logic level.

### Claim 19 (depends on 17)

The method as claimed in claim 17, wherein said enable signal is active for said N2 counter when said enable signal is a low logic level, and said enable signal is inactive for said N2 counter when said enable signal is a high logic level.

### Claim 20 (depends on 17)

The method as claimed in claim 17, wherein said N1 counter is a fixed counter.

### Claim 21 (depends on 17)

The method as claimed in claim 17, wherein said N1 counter is a programmable counter.

### Claim 22 (depends on 17)

The method as claimed in claim 17, wherein said processor comprises:
a programmed holding register for storing a value of a target frequency programmed by an external control device and delivering an output data;
a DAC holding register for delivering an output data coupled to said output signal of said processor;
a first arithmetic logic unit (ALU) for subtracting said output signal of said N2 counter from said output data of said programmed holding register and delivering an output data; and
a second ALU for adding said output data of said DAC holding register to said output data of said first ALU and delivering an output data to said DAC holding register;
wherein said DAC holding register further comprises an input Hold/Update port to set said DAC holding register in a Hold or Update mode; and said output data of said DAC holding register is not changed in said Hold mode.

### Claim 23

A method for constructing a frequency synthesizer having an N1 counter, an N2 counter, a processor, a memory, a DAC, and a VCO, the method comprising the steps of:
inputting a reference frequency to said N1 counter as a time base for said frequency synthesizer;
driving said N1 counter to generate an enable signal by dividing said reference frequency by a number of N1;
driving said N2 counter to generate an output data coupled to said processor by dividing an output frequency by a number of N2 when said enable signal is active;
driving said processor to generate an output data coupled to said memory as a memory address;
driving said memory to generate an output data coupled to a DAC register of said DAC;
driving said DAC to generate an analog output signal coupled to a VCO by said output data of said DAC register; and
driving said VCO to generate said output frequency coupled to said N2 counter.

### Claim 24 (depends on 23)

The method as claimed in claim 23, wherein said processor comprises:
a programmed holding register for storing a value of a target frequency programmed by an external control device and delivering an output data;
a DAC holding register for receiving said output data of said programmed holding register, and delivering an output data coupled to said output signal of said processor;
a first arithmetic logic unit (ALU) for subtracting said output data of said N2 counter from said output data of said programmed holding register, and delivering an output data; and
a second ALU for adding said output data of said DAC holding register to said output data of said first ALU, and delivering an output data to said DAC holding register;
wherein said DAC holding register further comprises an input Hold/Update port to set said DAC holding register in a Hold or Update mode; and said output data of said DAC holding register is not changed in said Hold mode.

### Claim 25 (depends on 23)

The method as claimed in claim 23, further comprising the steps of:
switching said DAC holding register of said processor to said Hold mode;
writing a value of said target frequency to said programmed holding register and said DAC register;
checking if said output frequency of said VCO matches said value stored in said programmed holding register as said target frequency;
loading a new value to sad DAC register and perform all operations for said DAC, VCO, and N2 counter until said output frequency matches said value stored in said programmed holding register;
reading said value stored in said DAC register and writing to said memory;
specifying a value of a new target frequency to said programmed holding register and said DAC register, and performing all operations for said N2 counter, processor, memory, DAC, and VCO until all values of target frequency are processed; and
switching said DAC holding register to said Update mode for normal frequency synthesizing operation according to said target frequency stored in said programmed holding register.