Comparator with low supply current spike and input offset cancellation
AssigneeTower Semiconductor Ltd.
InventorsErez Sarig, Raz Reshef
Life of this patent
Estimating the term…
Abstract
A current control circuit is coupled in parallel with the current paths of a differential comparator circuit to ensure that a substantially constant current is drawn from a current source during all operating phases of a comparator. The current control circuit is biased by a reference voltage, which is also used to bias a V− input terminal of the differential comparator circuit. The reference voltage is stored by a sample capacitor, which is charged by applying the reference voltage to a V+ input terminal of the differential comparator circuit while coupling an output terminal of the differential comparator circuit to the sample capacitor in a unity feedback configuration.
Claims18
A comparator comprising:
- a current source that provides a source current to a first node;
- a first voltage supply terminal configured to receive a first supply voltage;
- a first transistor coupled between the first node and the first voltage supply terminal along a first current path;
- a second transistor coupled between the first node and the first voltage supply terminal along a second current path;
- a third transistor coupled between the first node and the first voltage supply terminal along a third current path, wherein the first, second and third current paths are separate and parallel current paths between the first node and the first voltage supply terminal;
- a first input terminal configured to receive a first differential input signal of the comparator, wherein the first input terminal is coupled to a gate of the first transistor;
- a second input terminal configured to receive a second differential input signal of the comparator, wherein the second input terminal is coupled to gates of the second and third transistors;
- a first capacitor coupled between the second input terminal and the first voltage supply terminal, wherein the first capacitor applies the second differential input signal to the comparator;
- and
- means for sampling the first differential input signal on the first capacitor.
A comparator comprising:
- a current source that provides a source current to a first node;
- a first voltage supply terminal configured to receive a first supply voltage;
- a first transistor coupled between the first node and the first voltage supply terminal along a first current path;
- a second transistor coupled between the first node and the first voltage supply terminal along a second current path;
- a third transistor coupled between the first node and the first voltage supply terminal along a third current path, wherein the first, second and third current paths are separate and parallel current paths between the first node and the first voltage supply terminal;
- a first input terminal configured to receive a first differential input signal of the comparator, wherein the first input terminal is coupled to a gate of the first transistor;
- a second input terminal configured to receive a second differential input signal of the comparator, wherein the second input terminal is coupled to gates of the second and third transistors;
- a first capacitor coupled between the second input terminal and the first voltage supply terminal, wherein the first capacitor applies the second differential input signal to the comparator;
- an output terminal configured to receive an output signal of the comparator, wherein the output terminal is coupled to a drain of the second transistor;
- and
- a switch coupled between the output terminal and the second input terminal.
A method of implementing a comparator comprising:
- sampling a reference voltage applied to a first input of a differential comparator circuit on a second input of the differential comparator circuit during a first operating phase;
- and then
- maintaining the reference voltage on the second input of the differential comparator circuit and an input of a current control circuit during a second operating phase, wherein the current control circuit provides a current path in parallel with current paths of the differential comparator circuit;
- and
- applying a ramp voltage to the first input of the differential comparator circuit during the second operating phase.
Dependencies are inferred from the claim text.