# US 7,609,091 B2 · Link transmitter with reduced power consumption

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- Number: US 7,609,091 B2
- Document ID: US7609091B2
- Status: Granted
- Kind: B2
- Application number: 11/240,585
- Filed: 2005-09-29
- Published: 2007-03-29
- Granted: 2009-10-27
- Earliest claimed: 2005-09-29
- Assignees: Intel Corporation
- Inventors: Harry Muljono; Stefan Rusu; Yanmei Tian; Mubeen Atha; David J. Ayers
- Web page: https://patentgrep.com/patent/US7609091B2

## CPC

- H04L 25/0276: {Arrangements for coupling common mode signals}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

With some transmitter embodiments disclosed herein, static power consumption in low power modes may be reduced without excessively increasing latency.

## Claims

### Claim 1

A chip, comprising:
a transmitter circuit to generate a differential signal and communicate it to a receiver, the transmitter to operate in an active mode where the differential signal has an associated common mode level and signal difference and in a low power mode where the signal has an associated common mode level that is less than the active mode common mode level and a signal difference sufficient to be perceived by the receiver.

### Claim 2 (depends on 1)

The chip of claim 1, in which the transmitter comprises drivers selectably and additively coupled to one another to generate the differential signal.

### Claim 3 (depends on 2)

The chip of claim 2, in which at least some of the drivers are gated off during the low power mode.

### Claim 4 (depends on 3)

The chip of claim 3, in which the drivers are differently weighted, the largest weighted driver remaining on to produce a signal difference when the transmitter is in the low power mode.

### Claim 5 (depends on 4)

The chip of claim 4, in which the drivers are binary weighted.

### Claim 6 (depends on 1)

The chip of claim 1, in which the transmitter comprises a one or more differential drivers to generate the differential signal and a bias generator to bias the one or more drivers at different levels during the active and low power modes.

### Claim 7 (depends on 6)

The chip of claim 6, in which the receiver includes an error detection circuit to enable the driver to be biased at a reduced level, using an initial training sequence, while in the active mode.

### Claim 8 (depends on 1)

The chip of claim 1, in which the transmitter can also operate in an idle mode having an associated common mode level that is close to the active mode common mode level and a signal difference approaching zero.

### Claim 9

A computer comprising:
a microprocessor chip having a transmitter circuit;
a wireless interface chip having a receiver to be linked to the microprocessor chip transmitter, the transmitter to generate a differential signal and communicate it to the receiver, the transmitter to operate in an active mode where the differential signal has an associated common mode level and signal difference and in a low power mode where the signal has an associated common mode level that is less than the active mode common mode level and a signal difference sufficient to be perceived by the receiver; and
an antenna coupled to the wireless interface chip to electromagnetically link it to a wireless network.

### Claim 10 (depends on 9)

The computer of claim 9, in which the transmitter comprises drivers selectably and additively coupled to one another to generate the differential signal.

### Claim 11 (depends on 10)

The computer of claim 10, in which at least some of the drivers are gated off during the low power mode.

### Claim 12 (depends on 11)

The computer of claim 11, in which the drivers are differently weighted, the largest weighted driver remaining on to produce a signal difference when the transmitter is in the low power mode.

### Claim 13 (depends on 12)

The computer of claim 12, in which the drivers are binary weighted.

### Claim 14 (depends on 10)

The computer of claim 10, in which the transmitter comprises a bias generator to bias the drivers at different levels during the active and low power modes.

### Claim 15

A chip, comprising:
a driver to generate a differential signal and communicate it to a receiver, the driver to operate in an active mode where the differential signal has an associated common mode level and signal difference and in a low power mode where the signal has an associated common mode level that is less than the active mode common mode level and a signal difference sufficient to be perceived by the receiver; and
a bias generator to bias the driver at different levels during the active and low power modes.

### Claim 16 (depends on 15)

The chip of claim 15, in which the driver comprises constituent drivers selectably and additively coupled to one another to generate the differential signal.

### Claim 17 (depends on 16)

The chip of claim 16, in which at least some of the constituent drivers are gated off during the low power mode.

### Claim 18 (depends on 17)

The chip of claim 17, in which the constituent drivers are differently weighted, the largest weighted driver remaining on to produce a signal difference when the transmitter is in the low power mode.

### Claim 19 (depends on 18)

The chip of claim 18, in which the constituent drivers are binary weighted.

### Claim 20 (depends on 15)

The chip of claim 15, in which the receiver includes an error detection circuit to enable the driver to be biased at a reduced level, using an initial training sequence, while in the active mode.