# US 7,609,089 B2 · FPGA architecture at conventional and submicron scales > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,609,089 B2 - Document ID: US7609089B2 - Status: Granted - Kind: B2 - Application number: 12/156,877 - Filed: 2008-06-04 - Published: 2008-10-02 - Granted: 2009-10-27 - Earliest claimed: 2006-01-31 - Assignees: Hewlett-Packard Development Company, L.P. - Inventors: Gregory S. Snider; Philip J. Kuekes - Web page: https://patentgrep.com/patent/US7609089B2 ## CPC - H03K 19/17748: Structural details of configuration resources - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - B82Y 30/00: Nanotechnology for materials or surface science, e.g. nanocomposites - G11C 8/10: Decoders - G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites} - G11C 13/0014: {comprising cells based on organic memory material} - H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables - H03K 19/1778: Structural details for adapting physical parameters - G11C 2213/15: Current-voltage curve - G11C 2213/34: Material includes an oxide or a nitride - G11C 2213/51: Structure including a barrier layer preventing or limiting migration, diffusion of ions or charges or formation of electrolytes near an electrode - G11C 2213/77: Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used - G11C 2213/81: Array wherein the array conductors, e.g. word lines, bit lines, are made of nanowires - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Reconfigurable logic devices and methods of programming the devices are disclosed. The logic device includes a look-up table (LUT) and at least one storage element configured for sampling LUT output signals. The LUT comprises a plurality of input signals, an array of programmable impedance devices operably coupled to the input signals, and the LUT output signals. Each programmable impedance device in the array includes a first electrode operably coupled to one of the input signal, a second electrode disposed to form a junction wherein the second electrode at least partially overlaps the first electrode, and a programmable material disposed between the first electrode and the second electrode. The programmable material operably couples the first electrode and the second electrode such that each programmable impedance device exhibits a non-volatile programmable impedance. The array may be configured as a one-dimensional or two-dimensional array. ## Claims ### Claim 1 A reconfigurable logic device, comprising: a look-up table (LUT), comprising: a plurality of LUT input signals; an address decoder operably coupled to the plurality of LUT input signals, the address decoder configured to generate a plurality of product terms; an array of programmable impedance devices operably coupled to the plurality of product terms, each programmable impedance device comprising: a first electrode operably coupled to one of the plurality of product terms; a second electrode disposed to form a junction wherein the second electrode at least partially overlaps the first electrode; and a programmable material disposed between the first electrode and the second electrode at least at the junction, the programmable material operably coupling the first electrode and the second electrode such that each programmable impedance device exhibits a non-volatile programmable impedance; at least one LUT output signal operably coupled to at least one of the array of programmable impedance devices; and at least one storage element configured for sampling the at least one LUT output signal. ### Claim 2 (depends on 1) The device of claim 1, wherein the non-volatile programmable impedance may be reconfigurably decreased by the application of voltage, current, or voltage and current with sufficient magnitude and direction, between the first electrode and the second electrode. ### Claim 3 (depends on 1) The device of claim 1, wherein the non-volatile programmable impedance may be reconfigurably increased by the application of voltage, current, or voltage and current with sufficient magnitude and sign, between the first electrode and the second electrode. ### Claim 4 (depends on 1) The device of claim 1, wherein the programmable material comprises a monolayer. ### Claim 5 (depends on 1) The device of claim 1, wherein the programmable material comprises a plurality of monolayers. ### Claim 6 (depends on 1) The device of claim 1, wherein the LUT further comprises at least one additional programmable impedance device configured as a redundant device and further configured to replace at least one programmable impedance device of the array of programmable impedance devices. ### Claim 7 (depends on 1) The device of claim 1, wherein the device is disposed on a substrate, the substrate including at least one conventional device selected from the group consisting of electronic devices, optical devices, mechanical devices, and combinations thereof.