# US 7,609,088 B2 · Programmable logic array

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- Number: US 7,609,088 B2
- Document ID: US7609088B2
- Status: Granted
- Kind: B2
- Application number: 11/295,634
- Filed: 2005-12-07
- Published: 2006-06-15
- Granted: 2009-10-27
- Earliest claimed: 2004-12-09
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Dong-Gyu Lee
- Web page: https://patentgrep.com/patent/US7609088B2

## CPC

- H03K 19/1772: {with synchronous operation of at least one of the logical matrixes}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A programmable logic array (PLA) which may include an AND-plane receiving first input signals and generating logic product signals based on the first input signals, and an OR-plane receiving the logic product signals and a second input signal and generating a logic sum signal based on the logic product signals.

## Claims

### Claim 1

A programmable logic array comprising:
an AND-plane receiving first input signals and generating logic product signals based on the first input signals; and
an OR-plane receiving the logic product signals and a delayed second input signal inputted later than the first input signals and generating a logic sum signal based on the logic product signals.

### Claim 2 (depends on 1)

The programmable logic array of claim 1, wherein the OR-plane includes:
a logic circuit varying the logic sum signal according to a logic state of the delayed second input signal.

### Claim 3 (depends on 1)

The programmable logic array of claim 1, wherein the OR-plane includes:
a logic circuit generating a first logic sum signal based on a first subset of the logic product signals, generating a second logic sum signal based on a second subset of the logic product signals, and
generating the logic sum signal by varying the first logic sum signal according to a logic state of the delayed second input signal and the second logic sum signal.

### Claim 4 (depends on 3)

The programmable logic array of claim 3, wherein the logic circuit includes:
a first output line transferring the first logic sum signal;
a second output line transferring the second logic sum signal;
a first enable circuit charging or discharging the first output line in synchronization with a first signal from the first subset of the logic product signals;
a second enable circuit charging or discharging the second output line in synchronization with a first signal from the second subset of the logic product signals;
a first transistor discharging the first output line based on a subset of the first subset of the logic product signals not including the first signal from the first subset;
a second transistor discharging the second output line based on a subset of the second subset of the logic product signals not including the first signal of the second subset;
a third enable circuit connecting the first output line and an output terminal, and charging or discharging the output terminal based on the first logic sum signal;
a first discharge device discharging the output terminal based on the second logic sum signal; and
a second discharge device discharging the output terminal based on the delayed second input signal.

### Claim 5 (depends on 4)

The programmable logic array of claim 4, wherein the first enable circuit includes:
a first inverter inverting the first signal from the first subset of the logic product signals;
a first PMOS transistor including a gate receiving an output of the first inverter, a source receiving a power voltage, and a drain connected to an internal node;
a first NMOS transistor including a drain connected to the output terminal, a source connected to a ground terminal, and a gate receiving the first signal from the first subset of the logic product signals;
a NAND gate including a first input terminal receiving an output of the first inverter and a second input terminal connected to the internal node;
a second PMOS transistor including a source receiving a power voltage, a drain connected to the output terminal, and a gate receiving an output of the NAND gate;
a second inverter receiving an output of the NAND gate: and
a second NMOS transistor including a gate receiving an output of the second inverter, a drain connected to the output terminal, and a source connected to the internal node.

### Claim 6 (depends on 4)

The programmable logic array of claim 4, wherein the second enable circuit includes:
a first inverter inverting the first signal from the second subset of the logic product signals;
a first PMOS transistor including a gate receiving an output of the first inverter, a source receiving a power voltage, and a drain connected to an internal node;
a first NMOS transistor including a drain connected to the output terminal, a source connected to a ground terminal, and a gate receiving the first signal from the second subset of the logic product signals;
a NAND gate including a first input terminal receiving an output of the first inverter and a second input terminal connected to the internal node;
a second PMOS transistor including a source receiving a power voltage, a drain connected to the output terminal, and a gate receiving an output of the NAND gate;
a second inverter receiving an output of the NAND gate; and
a second NMOS transistor including a gate receiving an output of the second inverter, a drain connected to the output terminal, and a source connected to the internal node.

### Claim 7 (depends on 4)

The programmable logic array of claim 4, wherein the third enable circuit includes:
a first inverter inverting the second logic sum signal;
a first PMOS transistor including a gate receiving the first logic sum signal, a source receiving a power voltage, and a drain connected to an internal node;
a first NMOS transistor including a drain connected to the output terminal, a source connected to a ground terminal, and a gate receiving an output of the first inverter;
a NAND gate including a first input terminal receiving the first logic sum signal and a second input terminal connected to the internal node;
a second PMOS transistor including a source receiving a power voltage, a drain connected to the output terminal, and a gate receiving an output of the NAND gate;
a second inverter receiving an output of the NAND gate; and
a second NMOS transistor including a gate receiving an output of the second inverter, a drain connected to the output terminal, and a source connected to the internal node.

### Claim 8 (depends on 4)

The programmable logic array of claim 4, wherein the OR-plane further includes an inverter for inverting an output signal of the output terminal.

### Claim 9

An OR-plane comprising:
a receiving circuit receiving logic product signals and an input signal; and
a generating circuit generating a logic sum signal based on the logic product signals, wherein the generating circuit includes,
a first logic sum generating circuit generating a first logic sum signal based on a first subset of the logic product signals;
a second logic sum generating circuit generating a second logic sum signal based on a second subset of the logic product signals; and
a logic sum generating circuit generating the logic sum signal by varying the first logic sum signal according to a logic state of the input signal and the second logic sum signal.

### Claim 10 (depends on 9)

The OR-plane of claim 9, wherein the first logic sum generating circuit includes:
a first output line transferring the first logic sum signal;
a first enable circuit charging or discharging the first output line in synchronization with a first signal from the first subset of the logic product signals;
a first transistor discharging the first output line based on a subset of the first subset of the logic product signals not including the first signal from the first subset; and
a third enable circuit connecting the first output line and an output terminal, and charging or discharging the output terminal based on the first logic sum signal; and
wherein the second logic sum generating circuit includes:
a second output line transferring the second logic sum signal;
a second enable circuit charging or discharging the second output line in synchronization with a first signal from the second subset of the logic product signals; and
a second transistor discharging the second output line based on a subset of the second subset of the logic product signals not including the first signal of the second subset; and
wherein the logic sum generating circuit comprises:
a first discharge device discharging the output terminal based on the second logic sum signal; and
a second discharge device discharging the output terminal based on the delayed second input signal.

### Claim 11 (depends on 10)

The OR-plane of claim 10, further comprising an inverter for inverting an output signal of the output terminal.

### Claim 12

A method of performing a logic function comprising:
receiving input signals including first input signals and a delayed second input signal inputted later than the first input signals;
generating logic product signals based on the first input signals;
generating a logic sum signal based on the logic product signals; and
varying the logic sum signal according to a logic state of the delayed second input signal.

### Claim 13 (depends on 12)

The method of performing a logic function of claim 12, wherein generating a logic sum signal includes:
generating a first logic sum signal based on a first subset of the logic product signals; and
generating a second logic sum signal based on a second subset of the logic product signals; and
wherein the varying the logic sum signal step comprises:
varying the first logic sum signal according to a logic state of the delayed second input signal and the second logic sum signal.

### Claim 14 (depends on 13)

The method of performing a logic function of claim 13, further comprising:
charging or discharging the first logic sum signal in synchronization with a first signal from the first subset of the logic product signals;
charging or discharging the second logic sum signal in synchronization with a first signal from the second subset of the logic product signals;
discharging the first logic sum signal based on a subset of the first subset of the logic product signals not including the first signal from the first subset;
discharging the second logic sum signal based on a subset of the second subset of the logic product signals not including the first signal of the second subset;
charging or discharging an output terminal based on the first logic sum signal;
discharging the output terminal based on the second logic sum signal; and
discharging the output terminal based on the delayed second input signal.

### Claim 15

A programmable logic array comprising:
an AND-plane receiving first input signals and generating logic product signals based on the first input signals; and
an OR-plane receiving the logic product signals and a delayed second input signal and generating a logic sum signal based on the logic product signals, wherein the OR-plane includes,
a logic circuit generating a first logic sum signal based on a first subset of the logic product signals, generating a second logic sum signal based on a second subset of the logic product signals, and generating the logic sum signal by varying the first logic sum signal according to a logic state of the delayed second input signal and the second logic sum signal.

### Claim 16

A method of performing a logic function comprising:
receiving input signals including first input signals and a delayed second input signal;
generating logic product signals based on the first input signals;
generating a logic sum signal based on the logic product signals; and
varying the logic sum signal according to a logic state of the delayed second input signal, wherein generating a logic sum signal includes,
generating a first logic sum signal based on a first subset of the logic product signals; and
generating a second logic sum signal based on a second subset of the logic product signals; and
wherein the varying the logic sum signal step includes,
varying the first logic sum signal according to a logic state of the delayed second input signal and the second logic sum signal.