# US 7,609,087 B1 · Integrated circuit device programming with partial power > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,609,087 B1 - Document ID: US7609087B1 - Status: Granted - Kind: B1 - Application number: 12/020,720 - Filed: 2008-01-28 - Granted: 2009-10-27 - Earliest claimed: 2002-08-29 - Assignees: Xilinx, Inc. - Inventors: Conrad A. Theron - Web page: https://patentgrep.com/patent/US7609087B1 ## CPC - H03K 19/17748: Structural details of configuration resources - G01R 31/318516: {Test of programmable logic devices [PLDs]} - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C 29/12005: {comprising voltage or current generators} - H03K 19/17736: Structural details of routing resources - H03K 19/17784: for supply voltage - H05K 1/029: {having a programmable lay-out, i.e. adapted for choosing between a few possibilities} - G11C 29/48: Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths - H05K 2201/10053: Switch - H05K 2201/10159: Memory - H05K 2201/10212: Programmable component - H05K 2201/10689: Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL] - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G11C: STATIC STORES (semiconductor memory devices H10B) - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract A separate program power input is provided to a programmable logic array's memory to permit it to be programmed independently of printed circuit board power. Means are provided to isolate the program power input from the array's programmable logic circuit. Means are further provided to isolate the memory from the programmable logic circuit. The program power is not connected directly or indirectly to the programmable logic circuit thereby permitting the use of low-power devices to program the memory without connecting the printed circuit board to a power supply. ## Claims ### Claim 1 A system, comprising: a printed circuit board; and a plurality of programmable devices, a first subset of the programmable devices configured for functioning in one of a board power supply mode and a separate program voltage mode, a second subset of the programmable devices configured for functioning in the board power supply mode and not configured for functioning in the separate program voltage mode, wherein the plurality of devices are mounted on the printed circuit board; and wherein for a test signal output from a first programmable device in the first subset and input to a second programmable device in the second subset, the second programmable device is configured to pass the test signal to an output pin of the second programmable device in response to the first programmable device functioning in the program voltage mode. ### Claim 2 (depends on 1) The system according to claim 1 wherein the plurality of programmable devices are coupled in series with respect to direction of test data flow. ### Claim 3 (depends on 2) The system according to claim 2 wherein the plurality of programmable devices forms a loop with respect to the direction of test data flow. ### Claim 4 (depends on 1) The system of claim 1, wherein: each programmable device in the first subset has a board power supply input and a program voltage input; each programmable device in the second subset has a board power supply input and does not have a program voltage input; the board power supply inputs are coupled to receive a board voltage level; and the program voltage inputs are coupled to receive one or more program voltage levels that are not equal to the board voltage level. ### Claim 5 (depends on 1) The system of claim 1, wherein the programmable device is selected from the group consisting of a field programmable gate array, a digital signal processor, a complex programmable logic device and a processor. ### Claim 6 A system, comprising: a printed circuit board; and a plurality of programmable devices, a first subset of the programmable devices configured for functioning in one of a board power supply mode and a separate program voltage mode, a second subset of the programmable devices configured for functioning in the board power supply mode and not configured for functioning in the separate program voltage mode, the second portion of the programmable devices being isolated during presence of the separate program voltage mode, wherein the plurality of devices are mounted on the printed circuit board; and wherein for a first programmable device in the first subset coupled to provide an input signal to a second programmable device in the second subset, the second programmable device is isolated from the first programmable device in response to the first programmable device functioning in the program voltage mode. ### Claim 7 (depends on 6) The system according to claim 6 wherein the plurality of programmable devices are coupled in series with respect to direction of test data flow. ### Claim 8 (depends on 7) The system according to claim 7 wherein the plurality of programmable devices forms a loop with respect to the direction test data flow. ### Claim 9 (depends on 4) The system of claim 4, further comprising a switch coupled to receive the test signal from the first programmable device, the switch configured to switch on and pass the test signal in response to the board voltage level being in a power-off state and the program voltage level for the first programmable device being in an active state.