# US 7,609,084 B2 · Output level stabilization circuit and CML circuit using the same

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- Number: US 7,609,084 B2
- Document ID: US7609084B2
- Status: Granted
- Kind: B2
- Application number: 12/032,208
- Filed: 2008-02-15
- Published: 2008-09-11
- Granted: 2009-10-27
- Earliest claimed: 2007-03-07
- Assignees: NEC Corporation
- Inventors: Yusuke Matsushima
- Web page: https://patentgrep.com/patent/US7609084B2

## CPC

- H03K 17/16: Modifications for eliminating interference voltages or currents
- H03K 17/162: {without feedback from the output circuit to the control circuit}
- H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor}
- H03K 2217/0027: Measuring means of, e.g. currents through or voltages across the switch
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An output level stabilization circuit being an output level stabilization circuit for a CML circuit, the output level stabilization circuit includes: a replica circuit constituted of transistors respectively having the same characteristics as one of differential-pair transistors of the CML circuit and a current source transistor; a comparison circuit which compares an output of the replica circuit with a reference voltage and supplies the comparison result as a control voltage for the current source transistor of the replica circuit; and a variable impedance circuit arranged between the output of the replica circuit and an input of the comparison circuit.

## Claims

### Claim 1

An output level stabilization circuit for a CML circuit, the output level stabilization circuit comprising:
a replica circuit comprising of transistors respectively having the same characteristics as one of differential-pair transistors of the CML circuit and a current source transistor;
a comparison circuit which compares an output of the replica circuit with a reference voltage and supplies the comparison result as a control voltage for the current source transistor of the replica circuit;
a variable impedance circuit arranged between the output of the replica circuit and an input of the comparison circuit;
a noise detection unit which detects a noise in the comparison result; and
a control unit which variably controls the impedance of the variable impedance circuit in response to the noise detection.

### Claim 2 (depends on 1)

The output level stabilization circuit according to claim 1, wherein the variable impedance circuit comprises a plurality of resistor devices connected in parallel, and a plurality of switching devices connected in series to the respective resistor devices; wherein the control unit performs on/off control of the switching device.

### Claim 3 (depends on 2)

The output level stabilization circuit according to claim 2, wherein the control unit is a counter which counts up or down in response to the noise detection unit, and an output of the counter performs on/off control of the switching device.

### Claim 4 (depends on 1)

A CML circuit comprising an output level stabilization circuit according to claim 1, wherein the comparison result is supplied to a control input of the current source transistor of the CML circuit.